VP 14 DD NC C NC 13 W
參數(shù)資料
型號(hào)： AD734BN
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 6/20頁(yè)
文件大小： 0K
描述： IC MULTIPLIER/DIVIDER 14-DIP
標(biāo)準(zhǔn)包裝： 1
功能： 模擬乘法器
位元/級(jí)數(shù)： 四象限
封裝/外殼： 14-DIP（0.300"，7.62mm）
供應(yīng)商設(shè)備封裝： 14-PDIP
包裝： 管件
AD734
Rev. E | Page 14 of 20
AD734
X1
1
X2
2
U0
3
U1
4
U2
5
VP 14
DD
NC
C
NC
13
W 12
Z1 11
Z2 10
Y2
7
ER 9
VN 8
Y1
6
L
+15V
R4
4.32k
R3
13k
R1
1.6k
R2
1.6k
–15V
0.1F
0
827
-00
9
Esinωt
E2 cos2ωt/10V
Figure 26. Frequency Doubler
OPERATION AS A DIVIDER
The AD734 supports two methods for performing analog
division. The first is based on the use of a multiplier in a
feedback loop. This is the standard mode recommended for
multipliers having a fixed scaling voltage, such as the AD534,
and is described in this section. The second uses the AD734’s
unique capability for externally varying the scaling (denominator)
voltage directly, and is described in the Division by Direct
Feedback Divider Connections
Figure 27 shows the connections for the standard (AD534)
divider mode. Feedback from the output, W, is now taken to the
Y2 (inverting) input, which, if the X input is positive, establishes a
negative feedback path. Y1 should normally be connected to the
ground associated with the load circuit, but can optionally be
used to sum a further signal to the output. If desired, the
polarity of the Y input connections can be reversed, with W
connected to Y1 and Y2 used as the optional summation input. In
this case, either the polarity of the X input connections must be
reversed or the X input voltage must be negative.
AD734
X1
1
X2
2
U0
3
U1
4
U2
5
VP 14
DD
NC
13
W 12
Z1 11
Z2 10
Y2
7
ER 9
VN 8
Y1
6
L
X INPUT
+0.1V TO
+10V
Y1
OPTIONAL
SUMMING
INPUT
±10V FS
+15V
Z INPUT
±10V FS
–15V
0.1F
W = 10
+Y1
(Z2 – Z1)
(X1 – X2)
00
82
7-
0
10
L
Figure 27. Standard (AD534) Divider Connection
The numerator input, which is differential and can have either
polarity, is applied to Pin Z1 and Pin Z2. As with all dividers
based on feedback, the bandwidth is directly proportional to
the denominator, being 10 MHz for X = 10 V and reducing to
100 kHz for X = 100 mV. This reduction in bandwidth, and
the increase in output noise (which is inversely proportional
to the denominator voltage) preclude operation much below a
denominator of 100 mV. Division using direct control of the
denominator (see Figure 29) does not have these shortcomings.
AD734
X1
1
X2
2
U0
3
U1
4
U2
5
VP 14
DD
NC
13
W 12
Z1 11
Z2 10
Y2
7
ER 9
VN 8
Y1
6
L
S
OPTIONAL
SUMMING
INPUT
±10V FS
+15V
Z INPUT
+10mV TO
+10V
–15V
0.1F
00
82
7-
0
11
L
D
–
+
W = (10V) (Z2 – Z1) + S
Figure 28. Connection for Square Rooting
Connections for Square-Rooting
The AD734 can be used to generate an output proportional to
the square root of an input using the connections shown in
Figure 28. Feedback is now via both the X and Y inputs, and is
always negative because of the reversed polarity between these
two inputs. The Z input must have the polarity shown, but
because it is applied to a differential port, either polarity of
input can be accepted with reversal of Z1 and Z2, if necessary.
The diode, D, which can be any small-signal type (1N4148
being suitable), is included to prevent a latching condition,
which can occur if the input is momentarily of the incorrect
polarity of the input. The output is always negative.
Note that the loading on the output side of the diode is provided
by the 25 kΩ of input resistance at X1 and Y2, and by the user’s
load. In high speed applications, it may be beneficial to include
further loading at the output (to 1 kΩ minimum) to speed up
response time. As in previous applications, a further signal, shown
in Figure 28 as S, can be summed to the output; if this option is
not used, this node should be connected to the load ground.
DIVISION BY DIRECT DENOMINATOR CONTROL
The AD734 can be used as an analog divider by directly varying
the denominator voltage. In addition to providing much higher
accuracy and bandwidth, this mode also provides greater
flexibility, because all inputs remain available. Figure 29 shows
the connections for the general case of a three-input multiplier
divider, providing the function
2
1
2
1
2
1
)
(
)
)(
(
Z
U
Y
X
W
+
=
(11)
where the
X, Y, and Z signals can all be positive or negative,
but the difference U = U1 U2 must be positive and in the range
10 mV to 10 V. If a negative denominator voltage must be used,
simply ground the noninverting input of the op amp. As previ-
ously noted, the X input must have a magnitude of less than 1.25U.
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AD734BNZ 功能描述:IC MULT/DIV 4-QUADRANT 14-DIP RoHS:是 類別:集成電路 (IC) >> 線性 - 模擬乘法器，除法器 系列:- 標(biāo)準(zhǔn)包裝:25 系列:HA 功能:模擬乘法器 位元/級(jí)數(shù):四象限 封裝/外殼:16-CDIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:16-CDIP 側(cè)面銅焊 包裝:管件
AD734BQ 功能描述:IC MULTIPLIER 4-QUADRANT 14-CDIP RoHS:否 類別:集成電路 (IC) >> 線性 - 模擬乘法器，除法器 系列:- 標(biāo)準(zhǔn)包裝:25 系列:HA 功能:模擬乘法器 位元/級(jí)數(shù):四象限 封裝/外殼:16-CDIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:16-CDIP 側(cè)面銅焊 包裝:管件
AD734SCHIPS 制造商:AD 制造商全稱:Analog Devices 功能描述:10 MHz, 4-Quadrant Multiplier/Divider
AD734SQ 制造商:AD 制造商全稱:Analog Devices 功能描述:10 MHz, Four-Quadrant Multiplier/Divider
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