參數(shù)資料
型號(hào)： AD7322BRUZ
廠商： Analog Devices Inc
文件頁數(shù)： 37/37頁
文件大?。?/td> 0K
描述： IC ADC 12BIT+ SAR 2CHAN 14TSSOP
標(biāo)準(zhǔn)包裝： 96
位數(shù)： 12
采樣率（每秒）： 1M
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 30mW
電壓電源： 雙 ±
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 14-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 14-TSSOP
包裝： 管件
輸入數(shù)目和類型： 2 個(gè)單端，單極；2 個(gè)單端，雙極；1 個(gè)差分，單極；1 個(gè)差分，雙極
產(chǎn)品目錄頁面： 777 (CN2011-ZH PDF)
配用： EVAL-AD7322CBZ-ND - BOARD EVALUATION FOR AD7322
AD7322
Data Sheet
Rev. B | Page 8 of 36
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
04863-
003
1
2
3
4
5
6
7
AD7322
14
13
12
11
10
9
8
DGND
DOUT
VDRIVE
VIN1
VDD
VCC
SCLK
TOP VIEW
(Not to Scale)
DIN
DGND
AGND
VIN0
VSS
REFIN/OUT
CS
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
CS
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on
the AD7322 and framing the serial data transfer.
2
DIN
Data Input. Data to be written to the on-chip registers is provided on this input and is clocked into the
register on the falling edge of SCLK (see the Registers section).
3, 13
DGND
Digital Ground. Ground reference point for all digital circuitry on the AD7322. The DGND and AGND
voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a
transient basis.
4
AGND
Analog Ground. Ground reference point for all analog circuitry on the AD7322. All analog input signals
and any external reference signal should be referred to this AGND voltage. The AGND and DGND
voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a
transient basis.
5
REFIN/OUT
Reference Input/Reference Output. The on-chip reference is available on this pin for use external to the
AD7322. The nominal internal reference voltage is 2.5 V, which appears at the pin. A 680 nF capacitor
should be placed on the reference pin (see the Reference section). Alternatively, the internal reference
can be disabled and an external reference applied to this input. On power-up, the external reference
mode is the default condition.
6
VSS
Negative Power Supply Voltage. This is the negative supply voltage for the analog input section.
7, 8
VIN0, VIN1
Analog Input 0 and Analog Input 1. The analog inputs are multiplexed into the on-chip track-and-hold.
The analog input channel for conversion is selected by programming the ADD0 channel address bit in
the control register. The inputs can be configured as single-ended, true differential, or pseudo differential
(see Table 10). The configuration of the analog inputs is selected by programming the mode bits,
Bit Mode 1 and Bit Mode 0, in the control register. The input range on each input channel is controlled by
programming the range register. Input ranges of ±10 V, ±5 V, ±2.5 V, and 0 V to +10 V can be selected
on each analog input channel when a +2.5 V reference voltage is used (see the Registers section).
9
VDD
Positive Power Supply Voltage. This is the positive supply voltage for the analog input section.
10
VCC
Analog Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for the ADC core on the AD7322.
This supply should be decoupled to AGND.
11
VDRIVE
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface
operates. This pin should be decoupled to DGND. The voltage at this pin may be different from that at
VCC, but it should not exceed VCC by more than 0.3 V.
12
DOUT
Serial Data Output. The conversion output data is supplied to this pin as a serial data stream. The bits
are clocked out on the falling edge of the SCLK input, and 16 SCLKs are required to access the data. The
data stream consists of two leading zero bits, a channel identification bit, the sign bit, and 12 bits of
conversion data. The data is provided MSB first (see the Serial Interface section).
14
SCLK
Serial Clock, Logic Input. A serial clock input provides the SCLK used for accessing the data from the
AD7322. This clock is also used as the clock source for the conversion process.
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