參數(shù)資料
型號: AD7314ARMZ-REEL7
廠商: Analog Devices Inc
文件頁數(shù): 2/8頁
文件大?。?/td> 170K
描述: IC SENSOR TEMP 10BIT DGTL 8-MSOP
標(biāo)準(zhǔn)包裝: 1,000
功能: 溫度監(jiān)控系統(tǒng)(傳感器)
傳感器類型: 內(nèi)部
感應(yīng)溫度: -35°C ~ 85°C
精確度: ±1°C
拓撲: ADC,寄存器庫
輸出類型: MICROWIRE?,QSPI?,SPI?
輸出警報:
輸出風(fēng)扇:
電源電壓: 2.65 V ~ 5.5 V
工作溫度: -35°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 8-MSOP
包裝: 帶卷 (TR)
REV. A
2
AD7314SPECIFICATIONS
*
(T
A
 = T
MIN
 to T
MAX
, V
DD
 = 2.65 V to 5.5 V, unless otherwise noted.)
Parameter
Min    Typ
Max
Unit
Test Conditions/Comments
TEMPERATURE SENSOR AND ADC
Accuracy
?.0
C
T
A
 = 35C to +85C. V
DD
 = 2.65 V to 2.9 V
?.0
C
T
A
 = 35C to +85C. V
DD
 = 3 V to 5.5 V
Resolution
10
Bits
Update Rate, t
R
400
ms
Temperature Conversion Time
25
ms
SUPPLIES
Supply Voltage
2.65
5.5
V
For Specified Performance
Supply Current
Normal Mode (Inactive)
250
300
mA
Part Not Converting, V
DD
 = 2.65 V to 2.9 V
275
mA
Part Not Converting, V
DD
 = 3 V to 5.5 V
Normal Mode (Active)
1
mA
Part Converting, V
DD
 = 2.65 V to 2.9 V
1.2
mA
Part Converting, V
DD
 = 3 V to 5.5 V
Shutdown Mode
1
mA
V
DD
 = 2.65 V to 2.9 V
1
mA
V
DD
 = 3 V to 5.5 V
Power Dissipation
860
mW
V
DD
 = 2.65 V. Using Normal Mode
(Auto Conversion)
Power Dissipation
V
DD
 = 2.65 V. Using Shutdown Mode
1 SPS
3
mW
10 SPS
3.3
mW
100 SPS
6
mW
DIGITAL INPUT
Input High Voltage, V
IH
1.85
V
V
DD
 = 2.65 V to 2.9 V
Input Low Voltage, V
IL
0.53
V
V
DD
 = 2.65 V to 2.9 V
Input High Voltage, V
IH
2.4
V
V
DD
 = 3 V to 5.5 V
Input Low Voltage, V
IL
0.8
V
V
DD
 = 3 V to 5.5 V
Input Current, I
IN
?
mA
V
IN
 = 0 V to V
DD
Input Capacitance, C
IN
10
pF
All Digital Inputs
DIGITAL OUTPUT
Output High Voltage, V
OH
2.4
V
I
SOURCE
 = I
SINK
= 200 mA
Output Low Voltage, V
OL
0.4
V
I
OL
 = 200 mA
Output Capacitance, C
OUT
50
pF
*All specifications apply for 35C to +85C, unless otherwise noted.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
1, 2
Parameter
Limit
Unit
Comments
t
1
0
ns min
CE to SCLK Setup Time
t
2
50
ns min
SCLK High Pulse Width
t
3
50
ns min
SCLK Low Pulse Width
t
4
4
35
ns max
Data Access Time after SCLK Rising Edge
t
5
20
ns min
Data Setup Time prior to SCLK Falling Edge
t
6
0
ns min
Data Hold Time after SCLK Falling Edge
t
7
0
ns min
CE to SCLK Hold Time
t
8
4
40
ns max
CE to SDO High Impedance
NOTES
1
Guaranteed by design and characterization, not production tested.
2
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and are timed from a voltage level of 1.6 V.
3
All specifications apply for 35C to +85C, unless otherwise noted.
4
Measured with the load circuit of Figure 2.
Specifications subject to change without notice.
(T
A
3
 = T
MIN
 to T
MAX
, V
DD
 = 2.65 V to 5.5 V, unless otherwise noted. See Figure 1.)
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