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參數(shù)資料
| 型號(hào)： | AD7304BR-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 19/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 8BIT QUAD R-R 16-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 設(shè)置時(shí)間： | 1µs |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 60mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電壓，單極；4 電壓，雙極 |
| 采樣率（每秒）： | 1M |
AD7304/AD7305
Rev. C | Page 8 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VOUTB 1
VOUTA 2
VSS 3
VREFA 4
VOUTC
16
VOUTD
15
VDD
14
VREFC
13
VREFB 5
VREFD
12
GND
6
SDI/SHDN
11
LDAC
7
CLK
10
CLR
8
CS
9
AD7304
TOP VIEW
(Not to Scale)
01114-008
Figure 8. AD7304 Pin Configuration
Table 7. AD7304 Pin Function Descriptions
Pin No.
Mnemonic
Description
1
VOUTB
Channel B Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to VREFB pin.
Output is open circuit when SHDN is enabled.
2
VOUTA
Channel A Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to VREFA pin.
Output is open circuit when SHDN is enabled.
3
VSS
Negative Power Supply Input. Specified range of operation is 0 V to
5.5 V.
4
VREFA
Channel A Reference Input. Establishes VOUTA full-scale voltage. Specified range of operation is VSS < VREFA < VDD.
5
VREFB
Channel B Reference Input. Establishes VOUTB full-scale voltage. Specified range of operation is VSS < VREFB < VDD.
6
GND
Common Analog and Digital Ground.
7
LDAC
Load DAC Register Strobe, Active Low. Simultaneously transfers data from all four input registers into the
corresponding DAC registers. Asynchronous active low input. DAC register is transparent when LDAC = 0. See
Table 4 for operation.
8
CLR
Clears All Input and DAC Registers to the Zero Condition. Asynchronous active low input. The serial register is
not effected.
9
CS
Chip Select, Active Low Input. Disables shift register loading when high. Transfers serial input register data to
the decoded input register when CS returns high. Does not effect LDAC operation.
10
CLK
Clock Input, Positive Edge Clocks Data into Shift Register. Disabled by chip select CS.
11
SDI/SHDN
Serial Data Input Loads Directly into the Shift Register, MSB First. Hardware shutdown (SHDN) control input,
active when pin is left floating by a three-state logic driver. Does not effect DAC register contents as long as
power is present on VDD.
12
VREFD
Channel D Reference Input. Establishes VOUTD full-scale voltage. Specified range of operation is VSS < VREFD < VDD.
13
VREFC
Channel C Reference Input. Establishes VOUTC full-scale voltage. Specified range of operation is VSS VREFC < VDD.
14
VDD
Positive Power Supply Input. Specified range of operation is 2.7 V to 5.5 V.
15
VOUTD
Channel D Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to VREFD pin.
Output is open circuit when SHDN is enabled.
16
VOUTC
Channel C Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to VREFC pin.
Output is open circuit when SHDN is enabled.
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