參數(shù)資料
型號(hào)： AD7276YUJZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 13/29頁(yè)
文件大小： 0K
描述： IC ADC 12BIT SGL 3MSPS TSOT-23-6
標(biāo)準(zhǔn)包裝： 3,000
位數(shù)： 12
采樣率（每秒）： 3M
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 19.8mW
電壓電源： 單電源
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： SOT-23-6 細(xì)型，TSOT-23-6
供應(yīng)商設(shè)備封裝： TSOT-23-6
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個(gè)單端，單極
配用： EVAL-AD7276CBZ-ND - BOARD EVALUATION FOR AD7276
AD7276/AD7277/AD7278
Rev. C | Page 19 of 28
To exit this mode of operation and power up the AD7276/
AD7277/AD7278, users should perform a dummy conversion.
On the falling edge of CS, the device begins to power up and
continues to power up as long as CS is held low until after the
falling edge of the 10th SCLK. The device is fully powered up
once 16 SCLKs elapse; valid data results from the next conversion,
as shown in
. If
CS is brought high before the 10th falling
edge of SCLK, the AD7276/AD7277/AD7278 go into full power-
down mode. Therefore, although the device can begin to power
up on the falling edge of CS, it powers down on the rising edge
of CS as long as this occurs before the 10th SCLK falling edge.
If the AD7276/AD7277/AD7278 are already in partial power-
down mode and CS is brought high before the 10th falling edge
of SCLK, the device enters full power-down mode. For more
information on the power-up times associated with partial
power-down mode in various configurations, see the
section.
Full Power-Down Mode
This mode is intended for use in applications where throughput
rates slower than those in the partial power-down mode are
required because power-up from a full power-down takes
substantially longer than that from a partial power-down. This
mode is suited to applications where a series of conversions
performed at a relatively high throughput rate are followed by a
long period of inactivity and thus, power down.
When the AD7276/AD7277/AD7278 are in full power-down
mode, all analog circuitry is powered down. To enter full power-
down mode, put the device into partial power-down mode by
bringing CS high between the second and 10
th falling edges of
SCLK. In the next conversion cycle, interrupt the conversion
process in the same way as shown in
by bringing
CS
high before the 10th SCLK falling edge. Once CS is brought high
in this window of SCLKs, the part powers down completely.
Note that it is not necessary to complete the 16 SCLKs once CS is
brought high to enter either of the power-down modes. Glitch
protection is not available when entering full power-down mode.
To exit full power-down mode and to power up the AD7276/
AD7277/AD7278, users should perform a dummy conversion,
similar to when powering up from partial power-down mode.
On the falling edge of CS, the device begins to power up and
continues to power up as long as CS is held low until after the
falling edge of the 10th SCLK. The required power-up time must
elapse before a conversion can be initiated, as shown in
.
See the
section for the power-up times
associated with the AD7276/AD7277/AD7278.
Power-Up Times
The AD7276/AD7277/AD7278 have two power-down modes,
partial power-down and full power-down, which are described
in detail in the Modes of Operation section. This section deals
with the power-up time required when coming out of either of
these modes.
To power up from partial power-down mode, one cycle is
required. Therefore, with an SCLK frequency of up to 48 MHz,
one dummy cycle is sufficient to allow the device to power up
from partial power-down mode. Once the dummy cycle is
complete, the ADC is fully powered up and the input signal is
acquired properly. The quiet time, tQUIET, must still be allowed
from the point where the bus goes back into three-state after the
dummy conversion to the next falling edge of CS.
To power up from full power-down, approximately 1 μs should
be allowed from the falling edge of CS, shown in
as
tPOWER UP.
Note that during power-up from partial power-down mode, the
track-and-hold, which is in hold mode while the part is
powered down, returns to track mode after the first SCLK edge,
following the falling edge of CS. This is shown as Point A in
When power supplies are first applied to the AD7276/AD7277/
AD7278, the ADC can power up in either of the power-down
modes or in normal mode. Because of this, it is best to allow a
dummy cycle to elapse to ensure that the part is fully powered
up before attempting a valid conversion. Likewise, if the part is
to be kept in partial power-down mode immediately after the
supplies are applied, then two dummy cycles must be initiated.
The first dummy cycle must hold CS low until after the 10th
SCLK falling edge; in the second cycle, CS must be brought high
between the second and 10th SCLK falling edges (see
Alternatively, if the part is to be placed into full power-down
mode when the supplies are applied, three dummy cycles must
be initiated. The first dummy cycle must hold CS low until after
the 10th SCLK falling edge; the second and third dummy cycles
place the part into full power-down mode (see
). See
the
section.
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