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參數(shù)資料
| 型號(hào)： | AD7266BSUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 3CHAN 2MSPS 32TQFP |
| 設(shè)計(jì)資源： | AD7266 SAR ADC in DC-Coupled Differential and Single-Ended Appls (CN0039) |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 2M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 33.6mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-TQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 12 個(gè)單端，單極；6 個(gè)差分，單極；6 個(gè)偽差分，單極 |
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AD7266
Rev. B | Page 26 of 28
APPLICATION HINTS
GROUNDING AND LAYOUT
The analog and digital supplies to the AD7266 are independent
and separately pinned out to minimize coupling between the
analog and digital sections of the device. The printed circuit
board (PCB) that houses the AD7266 should be designed so
that the analog and digital sections are separated and confined
to certain areas of the board. This design facilitates the use of
ground planes that can be easily separated.
To provide optimum shielding for ground planes, a minimum
etch technique is generally best. All three AGND pins of the
AD7266 should be sunk in the AGND plane. Digital and analog
ground planes should be joined in only one place. If the AD7266
is in a system where multiple devices require an AGND to DGND
connection, the connection should still be made at one point
only, a star ground point that should be established as close as
possible to the ground pins on the AD7266.
Avoid running digital lines under the device as this couples
noise onto the die. However, the analog ground plane should be
allowed to run under the AD7266 to avoid noise coupling. The
power supply lines to the AD7266 should use as large a trace as
possible to provide low impedance paths and reduce the effects
of glitches on the power supply line.
To avoid radiating noise to other sections of the board, fast
switching signals, such as clocks, should be shielded with digital
ground, and clock signals should never run near the analog
inputs. Avoid crossover of digital and analog signals. To reduce
the effects of feedthrough within the board, traces on opposite
sides of the board should run at right angles to each other. A
microstrip technique is the best method but is not always
possible with a double-sided board. In this technique, the
component side of the board is dedicated to ground planes,
while signals are placed on the solder side.
Good decoupling is also important. All analog supplies should
be decoupled with 10 μF tantalum capacitors in parallel with
0.1 μF capacitors to GND. To achieve the best results from these
decoupling components, they must be placed as close as
possible to the device, ideally right up against the device. The
0.1 μF capacitors should have low effective series resistance
(ESR) and effective series inductance (ESI), such as the
common ceramic types or surface-mount types. These low ESR
and ESI capacitors provide a low impedance path to ground at
high frequencies to handle transient currents due to internal
logic switching.
PCB DESIGN GUIDELINES FOR LFCSP
The lands on the chip scale package (CP-32-3) are rectangular.
The PCB pad for these should be 0.1 mm longer than the
package land length, and 0.05 mm wider than the package land
width, thereby having a portion of the pad exposed. To ensure
that the solder joint size is maximized, the land should be
centered on the pad.
The bottom of the chip scale package has a thermal pad. The
thermal pad on the PCB should be at least as large as the
exposed pad. On the PCB, there should be a clearance of at least
0.25 mm between the thermal pad and the inner edges of the
pad pattern to ensure that shorting is avoided.
To improve thermal performance of the package, use thermal
vias on the PCB incorporating them in the thermal pad at
1.2 mm pitch grid. The via diameter should be between 0.3 mm
and 0.33 mm, and the via barrel should be plated with 1 oz.
copper to plug the via. The user should connect the PCB
thermal pad to AGND.
EVALUATING THE AD7266 PERFORMANCE
The recommended layout for the AD7266 is outlined in the
evaluation board documentation. The evaluation board package
includes a fully assembled and tested evaluation board, docu-
mentation, and software for controlling the board from the PC
via the evaluation board controller. The evaluation board con-
troller can be used in conjunction with the AD7266 evaluation
board, as well as many other Analog Devices, Inc. evaluation
boards ending in the CB designator, to demonstrate/evaluate
the ac and dc performance of the AD7266.
The software allows the user to perform ac (fast Fourier
transform) and dc (histogram of codes) tests on the AD7266.
The software and documentation are on a CD shipped with the
evaluation board.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7273 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3MSPS,10-/12-Bit ADCs in 8-Lead TSOT |
| AD72731 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3 MSPS,10-/12-Bit ADCs in 8-Lead TSOT |
| AD7273BRM | 制造商:AD 制造商全稱:Analog Devices 功能描述:3MSPS,10-/12-Bit ADCs in 8-Lead TSOT |
| AD7273BRMZ | 功能描述:IC ADC 10BIT 3MSPS HS LP 8MSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD7273BRMZ2 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3 MSPS,10-/12-Bit ADCs in 8-Lead TSOT |
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