參數(shù)資料
型號(hào)： AD7265ASU
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： Differential Input, Dual 1 MSPS, 12-Bit, 3-Channel SAR ADC
中文描述： DUAL 3-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PQFP32
封裝： MS-026ABA, TQFP-32
文件頁(yè)數(shù)： 7/16頁(yè)
文件大小： 706K
代理商： AD7265ASU
Preliminary Technical Data
AD7265
Pin No.
21
Mnemonic
RANGE
Description
Analog Input Range Selection. Logic input. The polarity on this pin will determine what input range the analog
input channels will have. On the falling edge of CS , the polarity of this pin is checked to determine the analog
input range of the next conversion. If this pin is tied to a logic low, the analog input range is 0 V to VREF. If this pin
is tied to a logic high when CS goes low, the analog input range is 2 × V
REF
.
Multiplexer Select. Logic inputs. Thess inputs are used to select the pair of channels to be converted
simultaneously, i.e., Channel 1 of both ADC A and ADC B, Channel 2 of both ADC A and ADC, and so on. The pair of
channels selected may be two single ended channels or two differential pairs. The logic states of these pins are
checked upon the falling edge of CS, and the multiplexer is set up for the next conversion. See Table 6 for
multiplexer address decoding.
Logic Input. This pin selects whether the analog inputs are configured as differential pairs or single ended. A logic
low selects differential operation while a logic high selects single ended operation.
Internal/External reference Selection. Logic Input. If this pin is tied to GND, the on-chip 2.5 V reference is used as
the reference source for both ADC A and ADC B. In addition, Pins D
CAP
A and D
CAP
B must be tied to decoupling
capacitors. If the REF SELECT pin is tied to a logic high, an external reference can be supplied to the AD7265
through the D
CAP
A and/or D
CAP
B pins.
25–23
A0–A2
22
SGL/DIFF
2
REF SELECT
Rev. PrA | Page 7 of 16
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