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參數(shù)資料
| 型號： | AD7249BR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Precision, Quad, SPST Analog Switches |
| 中文描述： | DUAL, SERIAL INPUT LOADING, 5 us SETTLING TIME, 12-BIT DAC, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 149K |
| 代理商： | AD7249BR |
AD7249
REV. C
–3–
TIMING CHARACTERISTICS
1, 2
Limit at T
MIN
to T
MAX
(All Versions)
Parameter
t
14
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
Unit
Conditions/Comments
200
15
50
0
150
0
20
0
50
20
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
SCLK Cycle Time
SYNC
to SCLK Falling Edge Setup Time
SYNC
to SCLK Hold Time
Data Setup Time
Data Hold Time
SYNC
High to
LDAC
Low
LDAC
Pulsewidth
LDAC
High to
SYNC
Low
CLR
Pulsewidth
SYNC
High Time
NOTES
1
Timing specifications guaranteed by design not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage
level of 1.6 V.
2
See Figure 8.
3
Power supply tolerance, A Version:
±
10%; B, S Versions:
±
5%.
4
SCLK Mark/Space Ratio range is 45/55 to 55/45.
(V
DD
= +12 V to +15 V,
3
V
SS
= 0 V or –12 V to –15 V,
3
AGND = DGND = 0 V, R
L
= 2 k
C
L
= 100 pF. All specifications T
MIN
to T
MAX
unless otherwise noted.)
,
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= +25
°
C unless otherwise noted)
V
DD
to AGND, DGND . . . . . . . . . . . . . . . . . . –0.3 V to +17 V
V
SS
to AGND, DGND . . . . . . . . . . . . . . . . . . +0.3 V to –17 V
AGND to DGND . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
V
OUTA, B2
to AGND . . . . . . . . . . . . V
SS
– 0.3 V to V
DD
+ 0.3 V
REFOUT to AGND . . . . . . . . . . . . . . . . . . . . . . . . 0 V to V
DD
REFIN to AGND . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Digital Inputs to DGND . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Industrial (A, B Versions) . . . . . . . . . . . . . .–40
°
C to +85
°
C
Extended (S Version) . . . . . . . . . . . . . . . . .–55
°
C to +125
°
C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150
°
C
Storage Temperature Range . . . . . . . . . . . . .–65
°
C to +150
°
C
Power Dissipation Plastic DIP . . . . . . . . . . . . . . . . . . .600 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . +117
°
C/W
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . +300
°
C
Power Dissipation, Cerdip . . . . . . . . . . . . . . . . . . . . . .600 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 76
°
C/W
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . +300
°
C
Power Dissipation, SOIC . . . . . . . . . . . . . . . . . . . . . . .600 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75
°
C/W
Lead Temperature (Soldering)
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . +215
°
C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . +220
°
C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one Absolute
Maximum Rating may be applied at any time.
2
The outputs may be shorted to voltages in this range provided the power dissipation
of the package is not exceeded.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7249 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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