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參數(shù)資料
| 型號(hào)： | AD7248ATQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | LC2MOS 12-Bit DACPORTs |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 12-BIT DAC, CDIP20 |
| 封裝： | 0.300 INCH, GLASS SEALED, CERDIP-20 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 306K |
| 代理商： | AD7248ATQ |
AD7245A/AD7248A
REV. A
–10–
the simultaneous updating of multiple AD7248A outputs. How-
ever, in systems where the asynchronous
LDAC
can occur dur-
ing a write cycle (or vice versa) care must be taken to ensure
that incorrect data is not latched through to the output. In other
words, if
LDAC
goes low while
WR
and either
CS
input are low
(or
WR
and either
CS
go low while
LDAC
is low), then the
LDAC
signal must stay low for t
7
or longer after
WR
returns
high to ensure correct data is latched through to the output.
T he write cycle timing diagram for the AD7248A is shown in
Figure 7.
Figure 7. AD7248A Write Cycle Timing Diagram
An alternate scheme for writing data to the AD7248A is to tie
the
CSMSB
and
LDAC
inputs together. In this case exercising
CSLSB
and
WR
latches the lower 8 bits into the input latch.
T he second write, which exercises
CSMSB
,
WR
and
LDAC
loads the upper 4-bit nibble to the input latch and at the same
time transfers the 12-bit data to the DAC latch. T his automatic
transfer mode updates the output of the AD7248A in two write
operations. T his scheme works equally well for
CSLSB
and
LDAC
tied together provided the upper 4-bit nibble is loaded to
the input latch followed by a write to the lower 8 bits of the in-
put latch.
T able II. AD7248A T ruth T able
CSLSB CSMSB WR
LDAC
Function
L
L
g
H
H
H
H
H
H
H
H
H
L
L
g
H
H
L
L
g
L
L
g
L
H
H
L
H
H
H
H
H
H
L
g
L
I.oad LS Byte into Input Latch
Latches LS Byte into Input Latch
Latches LS Byte into Input Latch
Loads MS Nibble into Input Latch
Latches MS Nibble into Input Latch
Latches MS Nibble into Input Latch
Loads Input Latch into DAC Latch
Latches Input Latch into DAC Latch
Loads MS Nibble into Input Latch and
Loads Input Latch into DAC Latch
No Data T ransfer Operation
H
H
H
H
H = High State L = Low State
APPLY ING T HE AD7245A/AD7248A
T he internal scaling resistors provided on the AD7245A/
AD7248A allow several output voltage ranges. T he part can
produce unipolar output ranges of 0 V to +5 V or 0 V to +10 V
and a bipolar output range of –5 V to +5 V. Connections for the
various ranges are outlined below.
UNIPOLAR (0 V T O +10 V) CONFIGURAT ION
T he first of the configurations provides an output voltage range
of 0 V to +10 V. T his is achieved by connecting the bipolar off-
set resistor, R
OFS
, to AGND and connecting R
FB
to V
OUT
.
In
this configuration the AD7245A/AD7248A can be operated
single supply (V
SS
= 0 V = AGND). If dual supply performance
is required, a V
SS
of –12 V to –15 V should be applied. Figure 8
shows the connection diagram for unipolar operation while the
table for output voltage versus the digital code in the DAC latch
is shown in T able III.
Figure 8. Unipolar (0 to +10 V) Configuration
T able III. Unipolar Code T able (0 V to +10 V Range)
DAC Latch Contents
MSB
LSB
Analog Output, V
OUT
1 1 1 1
1 1 1 1
1 1 1 1
+2
V
REF
3
4095
4096
1 0 0 0
0 0 0 0
0 0 0 1
+2
V
REF
3
2049
4096
1 0 0 0
0 0 0 0
0 0 0 0
+2
V
REF
3
2048
4096
= +
V
REF
0 1 1 1
1 1 1 1
1 1 1 1
+2
V
REF
3
2047
4096
0 0 0 0
0 0 0 0
0 0 0 1
+2
V
REF
3
1
4096
0 0 0 0
0 0 0 0
0 0 0 0
0 V
NOT E:
1
LSB
= 2
3
V
REF
(2
–12
) =
V
REF
1
2048
UNIPOLAR (0 V T O +5 V) CONFIGURAT ION
T he 0 V to +5 V output voltage range is achieved by tying R
OFS
,
R
FB
and V
OUT
together. For this output range the AD7245A/
AD7248A can be operated single supply (V
SS
= 0 V) or dual
supply. T he table for output voltage versus digital code is as in
T able III, with 2 V
REF
replaced by V
REF
. Note that for this
range
1
LSB
=
V
REF
(2
–12
) =
V
REF
3
1
4096
.
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