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參數(shù)資料
| 型號： | AD7248ABN |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT W/REF 24-DIP |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標準包裝： | 18 |
| 系列： | DACPORT® |
| 設置時間： | 7µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 210mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 24-DIP（0.300"，7.62mm） |
| 供應商設備封裝： | 24-PDIP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | 142k |
AD7245A/AD7248A
REV. B
–13–
Table V. Sample Program for Loading AD7245A from 8086
ASSUME DS: DACLOAD, CS: DACLOAD
DACLOAD SEGMENT AT 000
00 8CC9
MOV CS,
: DEFINE DATA SEGMENT
CS
REGISTER
02 8ED9
MOV DS,
: EQUAL TO CODE
CX
SEGMENT REGISTER
04 BF00D0
0MOV DI,
: LOAD DI WITH D000
#D000
07 C705
MOV MEM, : DAC LOADED WITH WXYZ
“YZWX” #YZWX
0B EA00 00
: CONTROL IS RETURNED TO
0E 00 FF
THE MONITOR PROGRAM
MC68000
AS
R/
W
D0–D15
ADDRESS
DECODE
ADDRESS BUS
*LINEAR CIRCUITRY OMITTED FOR CLARITY
DATA BUS
AD7245A*
CS
LDAC
WR
DB11
DB0
DTACK
Figure 14. AD7245A to MC68000 Interface
Table VI. Sample Routine for Loading AD7245A from 68000
01000
MOVE.W
#X,D0
The desired DAC data,
X, is loaded into Data
Register 0. X may be any
value between 0 and 4094
(decimal) or 0 and OFFF
(hexadecimal).
MOVE.W
D0,$E000
The Data X is transferred
between D0 and the
DAC Latch.
MOVE.B
#228,D7
Control is returned to
the System Monitor
Program using these two
TRAP
#14
instructions.
MICROPROCESSOR INTERFACE—AD7248A
Figure 15 shows the connection diagram for interfacing the
AD7248A to both the 8085A and 8088 microprocessors. This
scheme is also suited to the Z80 microprocessor, but the Z80
address/data bus does not have to be demultiplexed. Data to be
loaded to the AD7248A is right justified. The AD7248A is
memory mapped with a separate memory address for the input
latch high byte, the input latch low byte and the DAC latch.
Data is first written to the AD7248A input latch in two write
operations. Either the high byte or the low byte data can be
written first to the AD7248A input latch. A write to the AD7248A
DAC latch address transfers the input latch data to the DAC
latch and updates the output voltage. Alternatively, the
LDAC
input can be asynchronous or can be common to a number
of AD7248As for simultaneous updating of a number of volt-
age channels.
A8–A15
ALE
WR
AD0–AD7
AD7248A*
OCTAL
LATCH
ADDRESS
DECODE
ADDRESS BUS
CSMSB
LDAC
WR
DB0–DB7
CSLSB
*LINEAR CIRCUITRY OMITTED FOR CLARITY.
ADDRESS/DATA BUS
8085A/8088
Figure 15. AD7248A to 8085A/8088 Interface
In a multiple DAC system the double buffering of the AD7245A
allows the user to simultaneously update all DACs. In Figure
13, a 12-bit word is loaded to the input latches of each of the
DACs in sequence. Then, with one instruction to the appropri-
ate address,
CS4 (i.e., LDAC) is brought LOW, updating all the
DACs simultaneously.
8086
ALE
WR
AD15
AD0
*LINEAR CIRCUITRY OMITTED FOR CLARITY
AD7245A*
16-BIT
LATCH
ADDRESS
DECODE
ADDRESS BUS
CS
LDAC
WR
DB11
DB0
AD7245A*
CS
LDAC
WR
DB11
DB0
AD7245A*
CS
LDAC
WR
DB11
DB0
CS1
DATA BUS
CS4
Figure 13. AD7245A to 8086 Multiple DAC Interface
AD7245A—MC68000 INTERFACE
Interfacing between the MC68000 and the AD7245A is accom-
plished using the circuit of Figure 14. Once again the AD7245A
is used in the single buffered mode. A software routine for load-
ing data to the AD7245A is given in Table VI. In this example
the AD7245A is located at address E000, and the 12-bit word is
written to the DAC in one MOVE instruction.
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| AD7248ABNZ | 功能描述:IC DAC 12BIT W/REF 24DIP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:DACPORT® 產(chǎn)品培訓模塊:Data Converter Fundamentals DAC Architectures 標準包裝:750 系列:- 設置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應商設備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
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