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參數(shù)資料
| 型號： | AD7248AAN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | LC2MOS 12-Bit DACPORTs |
| 中文描述： | PARALLEL, 8 BITS INPUT LOADING, 7 us SETTLING TIME, 12-BIT DAC, PDIP20 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-20 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 306K |
| 代理商： | AD7248AAN |
AD7245A/AD7248A
REV. A
–11–
BIPOLAR CONFIGURAT ION
T he bipolar configuration for the AD7245A/AD7248A, which
gives an output voltage range from –5 V to +5 V, is achieved by
connecting the R
OFS
input to REF OUT and connecting R
FB
and V
OUT
. T he AD7245A/AD7248A must be operated from
dual supplies to achieve this output voltage range. T he code
table for bipolar operation is shown in T able IV.
T able IV. Bipolar Code T able
DAC Latch Contents
MSB
LSB
Analog Output, V
OUT
1 1 1 1
1 1 1 1
1 1 1 1
+
V
REF
×
2047
2048
1 0 0 0
0 0 0 0
0 0 0 1
+
V
REF
×
1
2048
1 0 0 0
0 0 0 0
0 0 0 0
0 V
0 1 1 1
1 1 1 1
1 1 1 1
–
V
REF
×
1
2048
0 0 0 0
0 0 0 0
0 0 0 1
–
V
REF
×
2047
2048
0 0 0 0
0 0 0 0
0 0 0 0
–
V
REF
×
2048
2048
=
±
V
REF
NOT E:
1
LSB
= 2
×
V
REF
(2
–11
) =
V
REF
1
2048
AGND BIAS
T he AD7245A/AD7248A AGND pin can be biased above sys-
tem GND (AD7245A/AD7248A DGND) to provide an offset
“zero” analog output voltage level. With unity gain on the am-
plifier (R
OFS
= V
OUT
= R
FB
) the output voltage, V
OUT
is ex-
pressed as:
V
OUT
= V
BIAS
+ D
3
V
REF
where D is a fractional representation of the digital word in the
DAC latch and V
BIAS
is the voltage applied to the AD7245A/
AD7248A AGND pin.
Because the current flowing out of the AGND pin varies with
digital code, the AGND pin should be driven from a low imped-
ance source. A circuit configuration is outlined for AGND bias
in Figure 9 using the AD589, a +1.23 V bandgap reference.
If a gain of 2 is used on the buffer amplifier the output voltage,
V
OUT
is expressed as
V
OUT
= 2(V
BIAS
+ D
3
V
REF
)
In this case care must be taken to ensure that the maximum out-
put voltage is not greater than V
DD
–3 V. T he V
DD
–V
OUT
over-
head must be greater than 3 V to ensure correct operation of the
part. Note that V
DD
and V
SS
for the AD7245A/AD7248A must
be referenced to DGND (system GND). T he entire circuit can
be operated in single supply with the V
SS
pin of the AD7245A/
AD7248A connected to system GND.
Figure 9. AGND Bias Circuit
PROGRAMMABLE CURRE NT SINK
Figure 10 shows how the AD7245A/AD7248A can be config-
ured with a power MOSFET transistor, the VN0300M, to pro-
vide a programmable current sink from V
DD
or V
SOURCE
. T he
VN0300M is placed in the feedback of the AD7245A/
AD7248A amplifier. T he entire circuit can be operated in single
supply by tying the V
SS
of the AD7245A/AD7248A to AGND.
T he sink current, I
SINK
, can be expressed as:
D
×
V
REF
I
SINK
=
R
1
Figure 10. Programmable Current Sink
Using the VN0300M, the voltage drop across the load can typi-
cally be as large as V
SOURCE
–6 V) with V
OUT
of the DAC at
+5 V. T herefore, for a current of 50 mA flowing in the R1 (with
all 1s in the DAC register) the maximum load is 200
with
V
SOURCE
= +15 V. T he VN0300M can actually handle currents
up to 500 mA and still function correctly in the circuit, but in
practice the circuit must be used with larger values of V
SOURCE
otherwise it requires a very small load.
Since the tolerance value on the reference voltage of the
AD7245A/AD7248A is
±
0.2%, then the absolute value of I
SINK
can vary by
±
0.2% from device to device for a fixed value of R1.
Because the input bias current of the AD7245A/AD7248A’s op
amp is only of the order of picoamps, its effect on the sink cur-
rent is negligible. T ying the R
OFS
input to R
FB
input reduces this
effect even further and prevents noise pickup which could occur
if the R
OFS
pin was left unconnected.
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