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參數(shù)資料
| 型號(hào)： | AD7247ABR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | LC2MOS Dual 12-Bit DACPORTs |
| 中文描述： | DUAL, PARALLEL, WORD INPUT LOADING, 5 us SETTLING TIME, 12-BIT DAC, PDSO24 |
| 封裝： | SOIC-24 |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 392K |
| 代理商： | AD7247ABR |
AD7237A/AD7247A
REV. 0
–4–
AD7237A PIN FUNCTION DESCRIPTION (DIP PIN NUMBERS)
Pin
Mnemonic
Description
1
REF INA
Voltage Reference Input for DAC A. The reference voltage for DAC A is applied to this pin. It is internally
buffered before being applied to the DAC. The nominal reference voltage for correct operation of the
AD7237A is 5 V.
2
REF OUT
Voltage Reference Output. The internal 5 V analog reference is provided at this pin. To operate the part with
internal reference, REF OUT should be connected to REF INA, REF INB.
3
REF INB
Voltage Reference Input for DAC B. The reference voltage for DAC B is applied to this pin. It is internally
buffered before being applied to the DAC. The nominal reference voltage for correct operation of the
AD7237A is 5 V.
4
R
OFSB
Output Offset Resistor for DAC B. This input configures the output ranges for DAC B. It is connected to
V
OUTB
for the +5 V range, to AGND for the +10 V range and to REF INB for the
±
5 V range.
5
V
OUTB
Analog Output Voltage from DAC B. This is the buffer amplifier output voltage. Three different output
voltage ranges can be chosen: 0 V to +5 V, 0 V to +10 V and
±
5 V. The amplifier is capable of developing
+10 V across a 2 k
resistor to GND.
6
AGND
Analog Ground. Ground reference for DACs, reference and output buffer amplifiers.
7
DB7
Data Bit 7.
8-10
DB6-DB4
Data Bit 6 to Data Bit 4.
11
DB3
Data Bit 3/Data Bit 11 (MSB).
12
DGND
Digital Ground. Ground reference for digital circuitry.
13
DB2
Data Bit 2/Data Bit 10.
14
DB1
Data Bit 1/Data Bit 9.
15
DB0
Data Bit 0 (LSB)/Data Bit 8.
16
A0
Address Input. Least significant address input for input latches. A0 and A1 select which of the four input
latches data is written to (see Table II).
17
A1
Address Input. Most significant address input for input latches.
18
CS
Chip Select. Active low logic input. The device is selected when this input is active.
19
WR
Write Input.
WR
is an active low logic input which is used in conjunction with
CS
, A0 and A1 to write data
to the input latches.
20
LDAC
Load DAC. Logic input. A new word is loaded into the DAC latches from the respective input latches on the
falling edge of this signal.
21
V
DD
Positive Supply (+12 V to +15 V).
22
V
OUTA
Analog Output Voltage from DAC A. This is the buffer amplifier output voltage. Three different output
voltage ranges can be chosen: 0 V to +5 V, 0 V to +10 V and
±
5 V. The amplifier is capable of developing
+10 V across a 2 k
resistor to GND.
23
V
SS
Negative Supply (0 V or –12 V to –15 V).
24
R
OFSA
Output Offset Resistor for DAC A. This input configures the output ranges for DAC A. It is connected to
V
OUTA
for the +5 V range, to AGND for the +10 V range and to REF INA for the
±
5 V range.
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