參數資料
型號: AD7244JRZ
廠商: Analog Devices Inc
文件頁數: 10/12頁
文件大?。?/td> 0K
描述: IC DAC 14BIT LC2MOS DUAL 28SOIC
產品培訓模塊: Data Converter Fundamentals
DAC Architectures
標準包裝: 1
設置時間: 4µs
位數: 14
數據接口: 串行
轉換器數目: 2
電壓電源: 雙 ±
功率耗散(最大): 195mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
供應商設備封裝: 28-SOIC W
包裝: 管件
輸出數目和類型: 2 電壓,雙極
采樣率(每秒): 250k
產品目錄頁面: 784 (CN2011-ZH PDF)
AD7242/AD7244
REV. A
–7–
Output Amplifier
The outputs from each of the voltage-mode DACs are buffered
by a noninverting amplifier. The buffer amplifier is capable of
developing
±3 V across a 2 k and 100 pF load to ground, and
can produce 6 V peak-to-peak sine wave signals to a frequency
of 20 kHz. The output is updated on the falling edge of the
respective LDAC input. The output voltage settling time, to
within 1/2 LSB of its final value, is typically less than 2
s for
the AD7242 and 2.5
s for the AD7244.
The small signal (200 mV p-p) bandwidth of the output buffer
amplifier is typically 1 MHz. The output noise from the
amplifier is low, with a figure of 30 nV/
√Hz at a frequency of
1 kHz. The broadband noise from the amplifier exhibits a
typical peak-to-peak figure of 150
V for a 1 MHz output
bandwidth. Figure 4 shows a typical plot of noise spectral
density versus frequency for the output buffer amplifier and for
the on-chip reference (including and excluding the decoupling
components).
Figure 4. Noise Spectral Density vs. Frequency
TRANSFER FUNCTION
The basic circuit configuration for the AD7242/AD7244 is
shown in Figure 5. Table I and Table II show the ideal input
code to output voltage relationship for the AD7242 and
AD7244 respectively. Input coding for the AD7242/AD7244 is
2s complement.
Figure 5. Basic Connection Diagram
For the AD7242, the output voltage can be expressed in terms
of the input code, N, using the following relationship:
VOUT =
2
N REF IN
4096
where –2048
≤ N ≤ +2047
For the AD7244, the output voltage can be expressed in terms
of the input code, N, using the following relationship:
VOUT =
2
N REF IN
16384
where –8192
≤ N ≤ +8191
Table I. AD7242 Ideal Input/Output Code Table Code
DAC Latch Contents
MSB
LSB
Analog Output, VOUT*
01 11 1111 1111
+2.998535 V
01 11 1111 1110
+2.99707 V
00 00 0000 0001
+0.001465 V
00 00 0000 0000
0 V
11 11 1111 1111
–0.001465 V
10 00 0000 0001
–2.998535 V
10 00 0000 0000
–3 V
*Assuming REF IN = +3 V.
Table II. AD7244 Ideal Input/Output Code Table Code
DAC Latch Contents
MSB
LSB
Analog Output, VOUT*
01 1111 1111 1111
+2.999634 V
01 1111 1111 1110
+2.99268 V
00 0000 0000 0001
+0.000366 V
00 0000 0000 0000
0 V
11 1111 1111 1111
–0.000366 V
10 0000 0000 0001
–2.999634 V
10 0000 0000 0000
–3 V
*Assuming REF IN = +3 V.
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