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參數(shù)資料
| 型號(hào)： | AD7243AQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | LC2MOS 12-Bit Serial DACPORT |
| 中文描述： | SERIAL INPUT LOADING, 5 us SETTLING TIME, 12-BIT DAC, CDIP16 |
| 封裝： | CERDIP-16 |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 171K |
| 代理商： | AD7243AQ |
REV. A
–11–
AD7243
Common clock, data, and synchronization signals are applied to
all DACs in the chain. The loading sequence starts by taking
SYNC
low. The data is then clocked into the input registers on
the falling edge of SCLK. Sixteen clock pulses are required for
each DAC in the chain. The data ripples through the input reg-
isters with the first 16-bit word filling the last register in the
chain after 16N clock pulses where N = the total number of
DACs in the chain.
When valid data has been loaded into all the registers, the
SYNC
input should be taken high and a common
LDAC
pulse
used to update all the DACs simultaneously.
APPLICATIONS
OPTO-ISOLATED INTERFACE
In many process control type applications it is necessary to pro-
vide an isolation barrier between the controller and the unit be-
ing controlled. Opto-isolators can provide voltage isolation in
excess of 3 kV. The serial loading structure of the AD7243
makes it ideal for opto-isolated interfaces as the number of in-
terface lines is kept to a minimum.
Figure 17 shows a 4-channel isolated interface using the
AD7243. The DCEN pin must be connected high to enable the
daisy-chain facility. Four channels with 12-bit resolution are
provided in the circuit shown, but this may be expanded to ac-
commodate any number of DAC channels without any extra
isolation circuitry.
The sequence of events to program the output channels is as
follows:
1. Take the
SYNC
line low.
2. Transmit the data as four 16-bit words. A total of 64 clock
pulses is required to clock the data through the chain.
3. Take the
SYNC
line high.
4. Pulse the
LDAC
line low. This updates all output channels
simultaneously on the falling edge of
LDAC
.
To reduce the number of opto-couplers, the
LDAC
line could
be driven from a one shot which is triggered by the rising edge
on the
SYNC
line. A low level pulse of 50 ns duration or greater
is all that is required to update the outputs.
SCLK
AD7243*
SYNC
LDAC
SDIN
DCEN
SDO
SCLK
AD7243*
SYNC
LDAC
SDIN
DCEN
SDO
SCLK
AD7243*
SYNC
LDAC
SDIN
DCEN
SDO
SCLK
AD7243*
SYNC
LDAC
SDIN
DCEN
SDO
V
OUT
*ADDITIONAL PINS OMITTED FOR CLARITY
DATA OUT
CLOCK OUT
SYNC OUT
CONTROL OUT
CONTROLLER
V
DD
V
OUT
(A)
QUAD OPTO-COUPLER
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
OUT
(B)
V
OUT
(C)
V
OUT
(D)
V
OUT
V
OUT
V
OUT
Figure 17. Four-Channel Opto-lsolated Interface
相關(guān)PDF資料 |
PDF描述 |
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| AD7243AR | LC2MOS 12-Bit Serial DACPORT |
| AD7243BN | 47 UF, 20V CAP., TANTALUM |
| AD7243BQ | LC2MOS 12-Bit Serial DACPORT |
| AD7243BR | SM IC/74HC08 SO-14 QUAD 2-IN |
| AD7243SQ2 | LC2MOS 12-Bit Serial DACPORT |
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