參數(shù)資料
型號(hào)： AD7233AN
廠商： ANALOG DEVICES INC
元件分類(lèi)： DAC
英文描述： ; Series:M; Thermistor Type:NTC; Resistance:100kohm; Package/Case:Radial; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; R/T Curve:4 RoHS Compliant: No
中文描述： SERIAL INPUT LOADING, 5 us SETTLING TIME, 12-BIT DAC, PDIP8
封裝： MINI, PLASTIC, DIP-8
文件頁(yè)數(shù)： 5/8頁(yè)
文件大?。?/td> 99K
代理商： AD7233AN
AD7233
REV. A
–5–
There are two ways in which the DAC latch and hence the ana-
log output may be updated. The status of the
LDAC
input is
examined after
SYNC
is taken low. Depending on its status, one
of two update modes is selected.
If
LDAC
= 0 then the automatic update mode is selected. In
this mode the DAC latch and analog output are updated auto-
matically when the last bit in the serial data stream is clocked in.
The update thus takes place on the sixteenth falling SCLK edge.
If
LDAC
= 1 then the automatic update is disabled and the
DAC latch is updated by taking
LDAC
low any time after the
16-bit data transfer is complete. The update now occurs on the
falling edge of
LDAC
. This facility is useful for simultaneous
update in multi-DAC systems. Note that the
LDAC
input must
be taken back high again before the next data transfer is initiated.
RESET
SCLK
–16
COUNTER/
DECODER
GATING
SIGNAL
GATED
SCLK
SDIN
INPUT SHIFT REGISTER (16 BITS)
DAC LATCH (12 BITS)
SYNC
LDAC
AUTO-UPDATE
CIRCUITRY
Figure 2. Simplified Loading Structure
SCLK
SDIN
t
4
t
1
t
3
t
2
t
5
DB15
DON'T CARE
DB0
LSB
SYNC
LDAC
DB11
MSB
DB14
DON'T CARE
DB13
DON'T CARE
DB12
DON'T CARE
t
6
t
7
t
8
≈
DB1
≈
≈
≈
≈
Figure 3. Timing Diagram
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