參數(shù)資料
型號(hào): AD722
廠商: Analog Devices, Inc.
英文描述: RGB to NTSC/PAL Encoder(RGB與NTSC/PAL制式轉(zhuǎn)換編碼器)
中文描述: RGB到的NTSC / PAL編碼器(與的RGB的NTSC / PAL制式轉(zhuǎn)換編碼器)
文件頁數(shù): 4/12頁
文件大?。?/td> 319K
代理商: AD722
REV. 0
–4–
AD722
PIN DESCRIPTIONS
Pin
Mnemonic
Description
Equivalent Circuit
1
STND
A Logical HIGH input selects NTSC encoding.
A Logical LOW input selects PAL encoding.
CMOS Logic Levels.
Analog Ground Connection.
FSC clock or parallel-resonant crystal, or 4FSC clock input.
For NTSC: 3.579 545 MHz or 14.318 180 MHz.
For PAL: 4.433 619 MHz or 17.734 480 MHz.
CMOS Logic Levels for subcarrier clocks.
Analog Positive Supply (+5 V
±
5%).
A Logical HIGH input enables the encode function.
A Logical LOW input powers down chip when not in use.
CMOS Logic Levels.
Red Component Video Input.
0 to 714 mV for NTSC; 0 to 700 mV for PAL.
Green Component Video Input.
0 to 714 mV for NTSC.
0 to 700 mV for PAL.
Blue Component Video Input.
0 to 714 mV for NTSC.
0 to 700 mV for PAL.
Chrominance Output (Subcarrier Only).*
Approximately 1.8 V peak-to-peak for both NTSC and PAL.
Composite Video Output.*
Approximately 2.5 V peak-to-peak for both NTSC and PAL.
Luminance plus SYNC Output.*
Approximately 2 V peak-to-peak for both NTSC and PAL.
A Logical LOW input selects the FSC operating mode.
A Logical HIGH input selects the 4FSC operating mode.
CMOS Logic Levels.
Digital Ground Connections.
Digital Positive Supply (+5 V
±
5%) .
Vertical Sync Signal (if using external CSYNC set at +5 V).
Horizontal Sync Signal (or CSYNC signal).
Circuit A
2
3
AGND
FIN
Circuit B
4
5
APOS
ENCD
Circuit A
6
RIN
Circuit C
7
GIN
Circuit C
8
BIN
Circuit C
9
CRMA
Circuit D
10
COMP
Circuit D
11
LUMA
Circuit D
12
SELECT
Circuit A
13
14
15
16
DGND
DPOS
VSYNC
HSYNC
Circuit A
Circuit A
*The Luminance, Chrominance, and Composite Outputs are at twice normal levels for driving 75
reverse-terminated lines.
Equivalent Circuits
5
1
12
15
16
DPOS
3
V
BIAS
APOS
10
9
11
APOS
7
V
CLAMP
6
8
APOS
4pF
TYP
Circuit B
Circuit D
Circuit C
Circuit A
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