參數(shù)資料
型號： AD7228ATQ3
廠商： Analog Devices, Inc.
英文描述： LC2MOS Octal 8-Bit DAC
中文描述： LC2MOS八進(jìn)制8位DAC
文件頁數(shù)： 2/8頁
文件大小： 207K
代理商： AD7228ATQ3
REV. A
–2–
AD7228A–SPECIFICATIONS
(V
DD
= 10.8 V to 16.5 V; V
SS
= –5 V
6
10%; GND = 0 V; V
REF
= +2 V to +10 V
1
; R
L
= 2 k
, C
L
= 100 pF unless otherwse
noted.) All specifications T
MN
to T
MAX
unless otherwse noted.
DUAL SUPPLY
5
Sample tested at 25
°
C to ensure compliance.
6
T he glitch impulse transferred to the output of one converter (not addressed) due to a
change in the digital input code to another addressed converter.
Specifications subject to change without notice.
(V
DD
= +15 V
6
10%, V
SS
; = GND = 0 V; V
REF
= +10 V, R
L
= 2 k
, C
L
= 100 pF unless otherwse noted.)
AII specifications T
MN
to T
MAX
unless otherwse noted.
B
Version
2
C
Version
T
Version
U
Version
Parameter
Units
Conditions/Comments
ST AT IC PERFORMANCE
Resolution
T otal Unadjusted Error
3
Relative Accuracy
Differential Nonlinearity
Full-Scale Error
4
Zero Code Error
@ 25
°
C
T
to T
Minimum Load Resistance
8
±
2
±
1
±
1
±
1
8
±
1
±
1/2
±
1
±
1/2
8
±
2
±
1
±
1
±
1
8
±
1
±
1/2
±
1
±
1/2
Bits
LSB max
LSB max
LSB max
LSB max
V
DD
= +15 V
±
10%, V
REF
= +10 V
Guaranteed Monotonic
T ypical tempco is 5 ppm/
°
C with V
REF
= +10 V
±
25
±
30
2
±
15
±
20
2
±
25
±
30
2
±
15
±
20
2
mV max
mV max
k
min
T ypical tempco is 30
μ
V/
°
C
V
OUT
= +10 V
REFERENCE INPUT
Voltage Range
1
Input Resistance
Input Capacitance
5
AC Feedthrough
2 to 10
2
500
–70
2 to 10
2
500
–70
2 to 10
2
500
–70
2 to 10
2
500
–7 0
V min/V max
k
min
pF max
dB typ
Occurs when each DAC is loaded with all 1s.
V
REF
= 8 V p-p Sine Wave @ 10 kHz
DIGIT AL INPUT S
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Leakage Current
Input Capacitance
Input Coding
DYNAMIC PERFORMANCE
5
Voltage Output Slew Rate
Voltage Output Settling T ime
Positive Full-Scale Change
Negative Full-Scale Change
Digital Feedthrough
Digital Crosstalk
2.4
0.8
±
1
8
Binary
2.4
0.8
±
1
8
Binary
2.4
0.8
±
1
8
Binary
2.4
0.8
±
1
8
Binary
V min
V max
μ
A max
pF max
V
IN
= 0 V or V
DD
2
2
2
2
V/
μ
s min
5
5
50
50
5
5
50
50
5
5
50
50
5
5
50
50
μ
s max
μ
s max
nV secs typ
nV secs typ
V
REF
= +10 V; Settling T ime to
±
1/2 LSB
V
= +10 V; Settling T ime to
±
1/2 LSB
Code transition all 0s to all 1s. V
REF
= 0 V;
WR
= V
Code transition all 0s to all 1s. V
REF
= +10 V;
WR
= 0 V
POWER SUPPLIES
V
DD
Range
V
SS
Range
I
DD
@ 25
°
C
T
MIN
to T
MAX
I
SS
@ 25
°
C
T
MIN
to T
MAX
10.8/16.5
–4.5/–5.5
10.8/16.5
–4.5/–5.5
10.8/16.5
–4.5/–5.5
10.8/16.5
–4.5/–5.5
V min/V max
V min/V max
For Specified Performance
For Specified Performance
Outputs Unloaded; V
IN
= V
INL
or V
INH
16
20
16
20
16
22
16
22
mA max
mA max
Outputs Unloaded; V
IN
= V
INL
or V
INH
14
18
14
18
14
20
14
20
mA max
mA max
SINGLE SUPPLY
ST AT IC PERFORMANCE
Resolution
T otal Unadjusted Error
3
Differential Nonlinearity
Minimum Load Resistance
8
±
2
±
1
2
8
±
1
±
1
2
8
±
2
±
1
2
8
±
1
±
1
2
Bits
LSB max
LSB max
k
min
Guaranteed Monotonic
V
OUT
= +10 V
REFERENCE INPUT
Input Resistance
Input Capacitance
5
2
500
2
500
2
500
2
500
k
min
pF max
Occurs when each DAC is loaded with all 1s.
DIGIT AL INPUT S
DYNAMIC PERFORMANCE
5
Voltage Output Slew Rate
Voltage Output Settling T ime
Positive Full-Scale Change
Negative Full-Scale Change
Digital Feedthrough
Digital Crosstalk
As per Dual Supply Specifications
2
2
2
2
V/
μ
s min
5
7
50
50
5
7
50
50
5
7
50
50
5
7
50
50
μ
s max
μ
s max
nV secs typ
nV secs typ
Settling T ime to
±
1/2 LSB
Settling T ime to
±
1/2 LSB
Code transition all 0s to all 1s. V
REF
= 0 V;
WR
= V
Code transition all 0s to all 1s. V
REF
= +10 V,
WR
= 0 V
POWER SUPPLIES
V
DD
Range
I
DD
@ 25
°
C
T
MIN
to T
MAX
13.5/16.5
13.5/16.5
13.5/16.5
13.5/16.5
V min/V max
For Specified Performance
Outputs Unloaded; V
IN
= V
INL
or V
INH
16
20
16
20
16
22
16
22
mA max
mA max
NOT ES
1
V
must be less than V
by 3.5 V to ensure correct operation.
2
T emperature ranges are as follows:
B, C Versions; –40
°
C to +85
°
C
T , U Versions; –55
°
C to +125
°
C
3
T otal Unadjusted Error includes zero code error, relative accuracy and full-scale error.
4
Calculated after zero code error has been adjusted out.
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