(VDD = 10.8 V to 16.5 V; VSS <" />
參數(shù)資料
型號(hào)： AD7228ABRZ
廠商： Analog Devices Inc
文件頁數(shù)： 2/8頁
文件大小： 0K
描述： IC DAC 8BIT LC2MOS OCTAL 24SOIC
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 31
設(shè)置時(shí)間： 5µs
位數(shù)： 8
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 8
電壓電源： 雙 ±
功率耗散（最大）： 310mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 24-SOIC W
包裝： 管件
輸出數(shù)目和類型： 8 電壓，單極；8 電壓，雙極
采樣率（每秒）： 200k
產(chǎn)品目錄頁面： 784 (CN2011-ZH PDF)
REV. A
–2–
AD7228A–SPECIFICATIONS
(VDD = 10.8 V to 16.5 V; VSS = –5 V
10%; GND = 0 V; VREF = +2 V to +10 V
1; R
L = 2 k
, C
L = 100 pF unless otherwise
noted.) All specifications TMIN to TMAX unless otherwise noted.
5Sample tested at 25
°C to ensure compliance.
6The glitch impulse transferred to the output of one converter (not addressed) due to a
change in the digital input code to another addressed converter.
Specifications subject to change without notice.
(VDD = +15 V
10%, VSS; = GND = 0 V; VREF = +10 V, RL = 2 k
, C
L = 100 pF unless otherwise noted.)
AII specifications TMIN to TMAX unless otherwise noted.
DUAL SUPPLY
BC
T
U
Parameter
Version
2
Version
Units
Conditions/Comments
STATIC PERFORMANCE
Resolution
8
Bits
Total Unadjusted Error
3
± 2
± 1
± 2
± 1
LSB max
VDD = +15 V ± 10%, VREF = +10 V
Relative Accuracy
± 1
± 1/2
± 1
± 1/2
LSB max
Differential Nonlinearity
± 1
LSB max
Guaranteed Monotonic
Full-Scale Error
4
± 1
± 1/2
± 1
± 1/2
LSB max
Typical tempco is 5 ppm/
°C with V
REF = +10 V
Zero Code Error
@ 25
°C
± 25
± 15
± 25
± 15
mV max
Typical tempco is 30
V/°C
TMIN to TMAX
± 30
± 20
± 30
± 20
mV max
Minimum Load Resistance
2
k
min
VOUT = +10 V
REFERENCE INPUT
Voltage Range
1
2 to 10
V min/V max
Input Resistance
2
k
min
Input Capacitance
5
500
pF max
Occurs when each DAC is loaded with all 1s.
AC Feedthrough
–70
–7 0
dB typ
VREF = 8 V p-p Sine Wave @ 10 kHz
DIGITAL INPUTS
Input High Voltage, VINH
2.4
V min
Input Low Voltage, VINL
0.8
V max
Input Leakage Current
± 1
A max
VIN = 0 V or VDD
Input Capacitance
5
8
pF max
Input Coding
Binary
DYNAMIC PERFORMANCE
5
Voltage Output Slew Rate
2
V/
s min
Voltage Output Settling Time
Positive Full-Scale Change
5
s max
VREF = +10 V; Settling Time to ± 1/2 LSB
Negative Full-Scale Change
5
s max
VREF = +10 V; Settling Time to ± 1/2 LSB
Digital Feedthrough
50
nV secs typ
Code transition all 0s to all 1s. VREF = 0 V; WR = VDD
Digital Crosstalk
6
50
nV secs typ
Code transition all 0s to all 1s. VREF = +10 V; WR = 0 V
POWER SUPPLIES
VDD Range
10.8/16.5
V min/V max
For Specified Performance
VSS Range
–4.5/–5.5
V min/V max
For Specified Performance
IDD
Outputs Unloaded; VIN = VINL or VINH
@ 25
°C
16
mA max
TMIN to TMAX
20
22
mA max
ISS
Outputs Unloaded; VIN = VINL or VINH
@ 25
°C
14
mA max
TMIN to TMAX
18
20
mA max
SINGLE SUPPLY
STATIC PERFORMANCE
Resolution
8
Bits
Total Unadjusted Error
3
± 2
± 1
± 2
± 1
LSB max
Differential Nonlinearity
± 1
LSB max
Guaranteed Monotonic
Minimum Load Resistance
2
k
min
VOUT = +10 V
REFERENCE INPUT
Input Resistance
2
k
min
Input Capacitance
5
500
pF max
Occurs when each DAC is loaded with all 1s.
DIGITAL INPUTS
As per Dual Supply Specifications
DYNAMIC PERFORMANCE
5
Voltage Output Slew Rate
2
V/
s min
Voltage Output Settling Time
Positive Full-Scale Change
5
s max
Settling Time to
±1/2 LSB
Negative Full-Scale Change
7
s max
Settling Time to
±1/2 LSB
Digital Feedthrough
50
nV secs typ
Code transition all 0s to all 1s. VREF = 0 V; WR = VDD
Digital Crosstalk
6
50
nV secs typ
Code transition all 0s to all 1s. VREF = +10 V, WR = 0 V
POWER SUPPLIES
VDD Range
13.5/16.5
V min/V max
For Specified Performance
IDD
Outputs Unloaded; VIN = VINL or VINH
@ 25
°C
16
mA max
TMIN to TMAX
20
22
mA max
NOTES
1V
OUT must be less than VDD by 3.5 V to ensure correct operation.
2Temperature ranges are as follows:
B, C Versions; –40
°C to +85°C
T, U Versions; –55
°C to +125°C
3Total Unadjusted Error includes zero code error, relative accuracy and full-scale error.
4Calculated after zero code error has been adjusted out.
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