參數資料
型號： AD7228ABP
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： LC2MOS Octal 8-Bit DAC
中文描述： OCTAL, PARALLEL, 8 BITS INPUT LOADING, 8-BIT DAC, PQCC28
封裝： PLASTIC, LCC-28
文件頁數： 3/8頁
文件大?。?/td> 207K
代理商： AD7228ABP
SWITCHINGCHARACTERISTICS
1, 2
Limit at 25
°
C
All Grades
Limit at T
, T
MAX
(B, C Versions)
Limit at T
, T
MAX
(T , U Versions)
Parameters
Units
Conditions/Comments
t
1
t
2
t
3
t
4
t
5
0
0
0
0
0
0
ns min
ns min
ns min
ns min
ns min
Address to
WR
Setup T ime
Address to
WR
Hold T ime
Data Valid to
WR
Setup T ime
Data Valid to
WR
Hold T ime
Write Pulse Width
70
10
95
90
10
120
100
10
150
NOT ES
1
Sample tested at 25
°
C to ensure compliance. All input rise and fall times measured from 10% to 90% of +5 V, t
R
= t
F
= 5 ns.
V
INH
+
V
INL
2
2
T iming measurement reference level is
INT E RFACE LOGIC INFORMAT ION
Address lines A0, A1 and A2 select which DAC accepts data
from the input port. T able I shows the selection table for the
eight DACs with Figure 1 showing the input control logic.
When the
WR
signal is low, the input latch of the selected DAC
is transparent, and its output responds to activity on the data
bus. T he data is latched into the addressed DAC latch on the
rising edge of
WR
. While
WR
is high, the analog outputs remain
at the value corresponding to the data held in their respective
latches.
T able I. AD7228A T ruth T able
AD7228A Control Inputs
WR
A2
AD7228A
Operation
A1
A0
H
X
X
X
No Operation
Device Not Selected
DAC 1 T ransparent
DAC 1 Latched
DAC 2 T ransparent
DAC 3 T ransparent
DAC 4 T ransparent
DAC 5 T ransparent
DAC 6 T ransparent
DAC 7 T ransparent
DAC 8 T ransparent
L
g
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
H
H
L
L
H
H
L
L
H
L
H
L
H
L
H
H = High State
L = Low State
X = Don’t Care
+5 V SUPPLY OPERATION
B
Version
C
Version
T
Version
U
Version
Parameter
Units
Conditions/Comments
ST AT IC PERFORMANCE
Resolution
Relative Accuracy
Differential Nonlinearity
Full-Scale Error
Zero Code Error
@ 25
°
C
T
MIN
to T
MAX
REFERENCE INPUT
Reference Input Range
8
±
2
±
1
±
4
8
±
2
±
1
±
2
8
±
2
±
1
±
4
8
±
2
±
1
±
2
Bits
LSB max
LSB max
LSB max
Guaranteed Monotonic
±
30
±
40
±
20
±
30
±
30
±
40
±
20
±
30
mV max
mV max
1.2
1.3
2
500
1.2
1.3
2
500
1.2
1.3
2
500
1.2
1.3
2
500
V min
V max
k
min
pF max
Reference Input Resistance
Reference Input Capacitance
POWER REQUIREMENT S
Positive Supply Range
Positive Supply Current
@ 25
°
C
T
to T
Negative Supply Current
@ 25
°
C
T
MIN
to T
MAX
4.75/5.25
4.75/5.25
4.75/5.25
4.75/5.25
V min/V max
For Specified Performance
16
20
16
20
16
22
16
22
μ
A max
μ
A max
14
18
14
18
14
20
14
20
μ
A max
μ
A max
NOT ES
All of the specifications as per Dual Supply Specifications except for negative full-scale settling-time when V
SS
= 0 V.
Specifications subject to change without notice.
(V
DD
= +5 V
6
5%, V
SS
; = 0 to –5 V
6
10%, GND = 0 V, V
REF
= +1.25 V, R
L
= 2 k
V
, C
L
= 100 pF
unless otherwse noted.) AII specifications T
MN
to T
MAX
unless otherwse noted.
(See Figures 1, 2; V
DD
= +5 V
6
5% or +10.8 V to +16.5 V; V
SS
= 0 V or –5 V
6
10%)
Figure 1. Input Control Logic
Figure 2. Write Cycle Timing Diagram
AD7228A
REV. A
–3–
相關PDF資料
PDF描述
AD7228ABQ LC2MOS Octal 8-Bit DAC
AD7228ABR LC2MOS Octal 8-Bit DAC
AD7228ACN LC2MOS Octal 8-Bit DAC
AD7228ACP LC2MOS Octal 8-Bit DAC
AD7228ACQ LC2MOS Octal 8-Bit DAC
相關代理商/技術參數
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