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| 型號(hào)： | AD7225LP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | DAC |
| 英文描述： | LC2MOS Quad 8-Bit DAC with Separate Reference Inputs |
| 中文描述： | PARALLEL, 8 BITS INPUT LOADING, 8-BIT DAC, PQCC28 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MO-047AB, LCC-28 |
| 文件頁(yè)數(shù)： | 3/12頁(yè) |
| 文件大小： | 339K |
| 代理商： | AD7225LP |
ORDE RING GUIDE
T otal
Unadjusted
E rror
T emperature
Range
Package
Option
2
Model
1
AD7225K N
AD7225LN
AD7225K P
AD7225LP
AD7225K R
AD7225LR
AD7225BQ
AD7225CQ
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
±
2 LSB
±
1 LSB
±
2 LSB
±
1 LSB
±
2 LSB
±
1 LSB
±
2 LSB
±
1 LSB
N-24
N-24
P-28A
P-28A
R-24
R-24
Q-24
Q-24
T otal
Unadjusted
E rror
T emperature
Range
Package
Option
2
Model
1
AD7225T Q
AD7225UQ
AD7225T E
AD7225UE
–55
°
C to +125
°
C
–55
°
C to +125
°
C
–55
°
C to +125
°
C
–55
°
C to +125
°
C
±
2 LSB
±
1 LSB
±
2 LSB
±
1 LSB
Q-24
Q-24
E-28A
E-28A
NOT ES
1
T o order MIL-ST D-883 processed parts, add /883B to part number. Contact your
local sales office for military data sheet.
2
E = Leadless Ceramic Chip Carrier; N = Plastic DIP;
P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC.
AD7225
REV. B
–3–
SINGLE SUPPLY
K, B
Versions
2
L, C
Versions
2
Parameter
T Version
U Version
Units
Conditions/Comments
ST AT IC PERFORMANCE
Resolution
T otal Unadjusted Error
3
Differential Nonlinearity
3
8
±
2
±
1
8
±
1
±
1
8
±
2
±
1
8
±
1
±
1
Bits
LSB max
LSB max
Guaranteed Monotonic
REFERENCE INPUT
Input Resistance
Input Capacitance
4
Channel-to-Channel Isolation
3, 4
AC Feedthrough
11
100
60
–70
11
100
60
–70
11
100
60
–70
11
100
60
–70
k
min
pF max
dB min
dB max
Occurs when each DAC is loaded with all 1s.
V
REF
= 10 V p-p Sine Wave @ 10 kHz
V
REF
= 10 V p-p Sine Wave @ 10 kHz
DIGIT AL INPUT S
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Leakage Current
Input Capacitance
Input Coding
2.4
0.8
±
1
8
Binary
2.4
0.8
±
1
8
Binary
2.4
0.8
±
1
8
Binary
2.4
0.8
±
1
8
Binary
V min
V max
μ
A max
pF max
V
IN
= 0 V or V
DD
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
4
Voltage Output Settling T ime
4
Positive Full-Scale Change
Negative Full-Scale Change
Digital Feedthrough
Digital Crosstalk
Minimum Load Resistance
2
2
2
2
V/
μ
s min
5
7
50
50
2
5
7
50
50
2
5
7
50
50
2
5
7
50
50
2
μ
s max
μ
s max
nV secs typ
nV secs typ
k
min
Settling T ime to
±
1/2 LSB
Settling T ime to
±
1/2 LSB
Code transition all 0s to all 1s.
Code transition all 0s to all 1s.
V
OUT
= +10 V
POWER SUPPLIES
V
DD
Range
I
DD
14.25/15.75
10
14.25/15.75
10
14.25/15.75
12
14.25/15.75
12
V min to V
max
mA max
For Specified Performance
Outputs Unloaded; V
IN
= V
INL
or V
INH
SWIT CHING CHARACT ERIST ICS
4
t
1
@ 25
°
C
T
MIN
to T
MAX
t
2
@ 25
°
C
T
MIN
to T
MAX
t
3
@ 25
°
C
T
MIN
to T
MAX
t
4
@ 25
°
C
T
MIN
to T
MAX
t
5
@ 25
°
C
T
MIN
to T
MAX
t
6
@ 25
°
C
T
MIN
to T
MAX
95
120
95
120
95
150
95
150
ns min
ns min
Write Pulse Width
0
0
0
0
0
0
0
0
ns min
ns min
Address to Write Setup T ime
0
0
0
0
0
0
0
0
ns min
ns min
Address to Write Hold T ime
70
90
70
90
70
90
70
90
ns min
ns min
Data Valid to Write Setup T ime
10
10
10
10
10
10
10
10
ns min
ns min
Data Valid to Write Hold T ime
95
120
95
120
95
150
95
150
ns min
ns min
Load DAC Pulse Width
NOT ES
1
Maximum possible reference voltage.
2
T emperature ranges are as follows:
K , L Versions: –40
°
C to +85
°
C
B, C Versions: –40
°
C to +85
°
C
T , U Versions: –55
°
C to +125
°
C
(V
DD
= +15 V
6
5%; V
SS
= AGND = DGND = OV; V
REF
= +10 V
1
unless otherwse noted.
All specifications T
MN
to T
MAX
unless otherwse noted.)
3
Sample T ested at 25
°
C to ensure compliance.
4
Switching characteristics apply for single and dual supply operation.
Specifications subject to change without notice.
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