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參數(shù)資料
| 型號(hào)： | AD7225KR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | LC2MOS Quad 8-Bit DAC with Separate Reference Inputs |
| 中文描述： | PARALLEL, 8 BITS INPUT LOADING, 8-BIT DAC, PDSO24 |
| 封裝： | ROHS COMPLIANT, MS-013AD, SOIC-24 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 339K |
| 代理商： | AD7225KR |
AD7225
REV. B
–9–
Figure 14. AD7225 Bipolar Output Circuit
T able IV. Bipolar (Offset Binary) Code T able
DAC Latch Contents
MSB
LSB
Analog Output
1 1 1 1
1 1 1 1
+
V
REF
127
128
1 0 0 0
0 0 0 1
+
V
REF
1
128
1 0 0 0
0 0 0 0
0 V
0 1 1 1
1 1 1 1
±
V
REF
1
128
0 0 0 0
0 0 0 1
±
V
REF
127
128
0 0 0 0
0 0 0 0
±
V
REF
128
128
±
V
REF
AGND BIAS
T he AD7225 AGND pin can be biased above system GND
(AD7225 DGND) to provide an offset “zero” analog output
voltage level. Figure 15 shows a circuit configuration to achieve
this for channel A of the AD7225. T he output voltage, V
OUT
A,
can be expressed as:
V
OUT
A
=
V
BIAS
+
D
A
(
V
IN
)
where
D
A
is a fractional representation of the digital word in
DAC latch A. (0
≤
D
A
≤
255/256).
Figure 15. AGND Bias Circuit
For a given V
IN
, increasing AGND above system GND will re-
duce the effective V
DD
–V
REF
which must be at least 4 V to en-
sure specified operation. Note that because the AGND pin is
common to all four DACs, this method biases up the output
voltages of all the DACs in the AD7225. Note that V
DD
and V
SS
of the AD7225 should be referenced to DGND.
AC RE FE RE NCE SIGNAL
In some applications it may be desirable to have ac reference
signals. T he AD7225 has multiplying capability within the up-
per (V
DD
– 4 V) and lower (2 V) limits of reference voltage when
operated with dual supplies. T herefore ac signals need to be ac
coupled and biased up before being applied to the reference in-
puts. Figure 16 shows a sine wave signal applied to V
REF
A. For
input signal frequencies up to 50 kHz the output distortion typi-
cally remains less than 0.1%. T he typical 3 dB bandwidth figure
for small signal inputs is 800 kHz.
Figure 16. Applying an AC Signal to the AD7225
APPLIC AT IONS
PROGRAMMABLE T RANSVE RSAL FILT E R
A discrete-time filter may be described by either multiplication
in the frequency domain or convolution in the time domain i.e.
Y
ω
( )
=
H
ω
( )
X
ω
( )
or
y
n
= ∑
T he convolution sum may be implemented using the special
structure known as the transversal filter (Figure 17). Basically, it
consists of an N-stage delay line with N taps weighted by N co-
efficients, the resulting products being accumulated to form the
output. T he tap weights or coefficients h
k
are actually the non-
zero elements of the impulse response and therefore determine
the filter transfer function. A particular filter frequency response
is realized by setting the coefficients to the appropriate values.
T his property leads to the implementation of transversal filters
whose frequency response is programmable.
=
1
N
h
kX n
±
k
+
1
Figure 17. Transversal Filter
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| AD7225KR-REEL | 功能描述:IC DAC 8BIT QUAD W/AMP 24-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時(shí)間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
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