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參數(shù)資料
| 型號： | AD7225CQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | LC2MOS Quad 8-Bit DAC with Separate Reference Inputs |
| 中文描述： | QUAD, PARALLEL, 8 BITS INPUT LOADING, 8-BIT DAC, CDIP24 |
| 封裝： | CERDIP-24 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 339K |
| 代理商： | AD7225CQ |
AD7225
REV. B
–6–
CIRCUIT INFORMAT ION
D/A SE CT ION
T he AD7225 contains four, identical, 8-bit voltage mode
digital-to-analog converters. Each D/A converter has a separate
reference input. T he output voltages from the converters have
the same polarity as the reference voltages, allowing single sup-
ply operation. A novel DAC switch pair arrangement on the
AD7225 allows a reference voltage range from +2 V to +12.5 V
on each reference input.
Each DAC consists of a highly stable, thin-film, R-2R ladder
and eight high speed NMOS, single-pole, double-throw
switches. T he simplified circuit diagram for channel A is shown
in Figure 7. Note that AGND (Pin 6) is common to all four
DACs.
Figure 7. D/A Simplified Circuit Diagram
T he input impedance at any of the reference inputs is code de-
pendent and can vary from 11 k
minimum to infinity. T he
lowest input impedance at any reference input occurs when that
DAC is loaded with the digital code 01010101. T herefore, it is
important that the reference presents a low output impedance
under changing load conditions. T he nodal capacitance at the
reference terminals is also code dependent and typically varies
from 15 pF to 35 pF.
Each V
OUT
pin can be considered as a digitally programmable
voltage source with an output voltage of:
V
OUT X
= D
X
V
REFX
where D
X
is fractional representation of the digital input code
and can vary from 0 to 255/256.
T he output impedance is that of the output buffer amplifier.
OP-AMP SE CT ION
Each voltage mode D/A converter output is buffered by a unity
gain noninverting CMOS amplifier. T his buffer amplifier is ca-
pable of developing +10 V across a 2 k
load and can drive ca-
pacitive loads of 3300 pF.
T he AD7225 can be operated single or dual supply; operating
with dual supplies results in enhanced performance in some pa-
rameters which cannot be achieved with single supply operation.
In single supply operation (V
SS
= 0 V = AGND) the sink capa-
bility of the amplifier, which is normally 400
μ
A, is reduced as
the output voltage nears AGND. T he full sink capability of
400
μ
A is maintained over the full output voltage range by tying
V
SS
to –5 V. T his is indicated in Figure 8.
Settling-time for negative-going output signals approaching
AGND is similarly affected by V
SS
. Negative-going settling-time
for single supply operation is longer than for dual supply opera-
tion. Positive-going settling-time is not affected by V
SS
.
Figure 8. Variation of I
SINK
with V
OUT
Additionally, the negative V
SS
gives more headroom to the out-
put amplifiers which results in better zero code performance and
improved slew rate at the output, than can be obtained in the
single supply mode.
DIGIT AL SE CT ION
T he AD7225 digital inputs are compatible with either T T L or
5 V CMOS levels. All logic inputs are static protected MOS
gates with typical input currents of less than 1 nA. Internal in-
put protection is achieved by an on-chip distributed diode be-
tween DGND and each MOS gate. T o minimize power supply
currents, it is recommended that the digital input voltages be
driven as close to the supply rails (V
DD
and DGND) as practi-
cally possible.
INT E RFACE LOGIC INFORMAT ION
T he AD7225 contains two registers per DAC, an input register
and a DAC register. Address lines A0 and A1 select which input
register will accept data from the input port. When the
WR
sig-
nal is LOW, the input latches of the selected DAC are transpar-
ent. T he data is latched into the addressed input register on the
rising edge of
WR
. T able I shows the addressing for the input
registers on the AD7225.
T able I. AD7225 Addressing
A1
A0
Selected Input Register
L
L
H
H
L
H
L
H
DAC A Input Register
DAC B Input Register
DAC C Input Register
DAC D Input Register
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