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參數(shù)資料
| 型號： | AD7225 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | ECONOLINE: REC2.2-S_DR/H1 - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- UL94V-0 Package Material- Continuous Short Circiut Protection- Internal SMD design- 100% Burned In- Efficiency to 75% |
| 中文描述： | LC2MOS四路8位DAC，帶有單獨(dú)的基準(zhǔn)輸入 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 339K |
| 代理商： | AD7225 |
AD7225
REV. B
–7–
Only the data held in the DAC register determines the analog
output of the converter. T he
LDAC
signal is common to all four
DACs and controls the transfer of information from the input
registers to the DAC registers. Data is latched into all four DAC
registers simultaneously on the rising edge of
LDAC
. T he
LDAC
signal is level triggered and therefore the DAC registers
may be made transparent by tying
LDAC
LOW (in this case the
outputs of the converters will respond to the data held in their
respective input latches).
LDAC
is an asynchronous signal and
is independent of
WR
. T his is useful in many applications.
However, in systems where the asynchronous
LDAC
can occur
during a write cycle (or vice versa) care must be taken to ensure
that incorrect data is not latched through to the output. In other
words, if
LDAC
is activated prior to the rising edge of
WR
(or
WR
occurs during
LDAC
), then
LDAC
must stay LOW for t
6
or longer after
WR
goes HIGH to ensure correct data is latched
through to the output. T able II shows the truth table for AD7225
operation. Figure 9 shows the input control logic for the part
and the write cycle timing diagram is given in Figure 10.
T able II. AD7225 T ruth T able
WR
LDAC
Function
H
L
g
H
H
H
H
L
No Operation. Device not selected
Input Register of Selected DAC T ransparent
Input Register of Selected DAC Latched
All Four DAC Registers T ransparent
(i.e. Outputs respond to data held in respective
input registers)
Input Registers are Latched
All Four DAC Registers Latched
DAC Registers and Selected Input Register
T ransparent Output follows Input Data for
Selected Channel.
H
L
g
L
Figure 9. Input Control Logic
Figure 10. Write Cycle Timing Diagram
GROUND MANAGE ME NT AND LAY OUT
Since the AD7225 contains four reference inputs which can be
driven from ac sources (see AC REFERENCE SIGNAL sec-
tion) careful layout and grounding is important to minimize
analog crosstalk between the four channels. T he dynamic per-
formance of the four DACs depends upon the optimum choice
of board layout. Figure 11 shows the relationship between input
Figure 11. Channel-to-Channel Isolation
Figure 12. Suggested PCB Layout for AD7225.
Layout Shows Component Side (Top View)
frequency and channel-to-channel isolation. Figure 12 shows a
printed circuit board layout which is aimed at minimizing
crosstalk and feedthrough. T he four input signals are screened
by AGND. V
REF
was limited to between 2 V and 3.24 V to
avoid slew rate limiting effects from the output amplifier during
measurements.
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