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參數(shù)資料
| 型號： | AD7224KR-1 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | LC2MOS 8-Bit DAC with Output Amplifiers |
| 中文描述： | PARALLEL, 8 BITS INPUT LOADING, 8-BIT DAC, PDSO20 |
| 封裝： | SOIC-20 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大小： | 228K |
| 代理商： | AD7224KR-1 |
AD7224
REV. B
–6–
T able I. AD7224 T ruth T able
RESET
H
H
H
H
H
H
H
L
LDAC
L
X
H
H
H
L
L
X
WR
L
H
X
L
g
L
g
X
CS
L
X
H
L
L
H
H
X
Function
Both Registers are T ransparent
Both Registers are Latched
Both Registers are Latched
Input Register T ransparent
Input Register Latched
DAC Register T ransparent
DAC Register Latched
Both Registers Loaded
With All Zeros
Both Register Latched With All Zeros
and Output Remains at Zero
Both Registers are T ransparent and
Output Follows Input Data
g
H
H
H
g
L
L
L
H = High State, L = Low State, X = Don’t Care.
All control inputs are level triggered.
T he contents of both registers are reset by a low level on the
RESET
line. With both registers transparent, the
RESET
line
functions like a zero override with the output brought to 0 V for
the duration of the
RESET
pulse. If both registers are latched, a
“LOW” pulse on
RESET
will latch all 0s into the registers and
the output remains at 0 V after the
RESET
line has returned
“HIGH”. T he
RESET
line can be used to ensure power-up to
0 V on the AD7224 output and is also useful, when used as a
zero override, in system calibration cycles. Figure 3 shows the
input control logic for the AD7224.
INPUT DATA
LDAC
WR
CS
RESET
DAC
REGISTER
INPUT
REGISTER
Figure 3. Input Control Logic
t
2
t
1
t
2
t
1
t
4
t
3
t
3
t
4
DATA
VALID
t
5
t
6
DATA
IN
CS
WR
LDAC
NOTES:
1. ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM 10% TO 90% OF V
DD
.
tr = tf = 20ns OVER V
DD
RANGE
. TIMING MEASUREMENT REFERENCE LEVEL IS
V
INH
+ V
INL
2
Figure 4. Write Cycle Timing Diagram
SPE CIFICAT ION RANGE S
For the DAC to maintain specified accuracy, the reference volt-
age must be at least 4 V below the V
DD
power supply voltage.
T his voltage differential is required for correct generation of bias
voltages for the DAC switches.
With dual supply operation, the AD7224 has an extended V
DD
range from +12 V
±
5% to +15 V
±
10% (i.e., from +11.4 V to
+16.5 V). Operation is also specified for a single V
DD
power
supply of +15 V
±
5%.
Performance is specified over a wide range of reference voltages
from 2 V to (V
DD
– 4 V) with dual supplies. T his allows a range
of standard reference generators to be used such as the AD580,
a +2.5 V bandgap reference and the AD584, a precision +10 V
reference. Note that in order to achieve an output voltage range
of 0 V to +10 V, a nominal +15 V
±
5% power supply voltage is
required by the AD7224.
GROUND MANAGE ME NT
AC or transient voltages between AGND and DGND can cause
noise at the analog output. T his is especially true in micropro-
cessor systems where digital noise is prevalent. T he simplest
method of ensuring that voltages at AGND and DGND are
equal is to tie AGND and DGND together at the AD7224. In
more complex systems where the AGND and DGND intertie is
on the backplane, it is recommended that two diodes be con-
nected in inverse parallel between the AD7224 AGND and
DGND pins (IN914 or equivalent).
Applying the AD7224
UNIPOLAR OUT PUT OPE RAT ION
T his is the basic mode of operation for the AD7224, with the
output voltage having the same positive polarity as V
REF
. T he
AD7224 can be operated single supply (V
SS
= AGND) or with
positive/negative supplies (see op-amp section which outlines
the advantages of having negative V
SS
). Connections for the uni-
polar output operation are shown in Figure 5. T he voltage at
V
REF
must never be negative with respect to DGND. Failure to
observe this precaution may cause parasitic transistor action and
possible device destruction. T he code table for unipolar output
operation is shown in T able II.
DAC
DB7
DB0
CS
WR
LDAC
3
V
DD
V
REF
RESET
V
SS
AGND
DGND
AD7224
V
OUT
DATA
(8-BIT)
Figure 5. Unipolar Output Circuit
T able III. Unipolar Code T able
DAC Register Contents
MSB
LSB
Analog Output
1 1 1 1
1 1 1 1
+
V
REF
255
256
1 0 0 0
0 0 0 1
+
V
REF
129
256
1 0 0 0
0 0 0 0
+
V
REF
128
256
= +
V
REF
2
0 1 1 1
1 1 1 1
+
V
REF
127
256
0 0 0 0
0 0 0 1
+
V
REF
1
256
0 0 0 0
0 0 0 0
0 V
Note
: 1
LSB
=
V
REF
(
)
2
8
(
)
=
V
REF
1
256
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