- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373893 > AD7224 (Analog Devices, Inc.) LC2MOS 8-Bit DAC with Output Amplifiers PDF資料下載
參數(shù)資料
| 型號(hào)： | AD7224 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | LC2MOS 8-Bit DAC with Output Amplifiers |
| 中文描述： | LC2MOS 8位DAC的輸出放大器 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 228K |
| 代理商： | AD7224 |
AD7224
REV. B
–5–
V
OUT
=
D
V
REF
where
D
is a fractional representation of the digital input code
and can vary from 0 to 255/256.
OP-AMP SE CT ION
T he voltage-mode D/A converter output is buffered by a unity
gain noninverting CMOS amplifier. T his buffer amplifier is
capable of developing +10 V across a 2 k
load and can drive
capacitive loads of 3300 pF.
T he AD7224 can be operated single or dual supply resulting in
different performance in some parameters from the output am-
plifier. In single supply operation (V
SS
= 0 V = AGND) the sink
capability of the amplifier, which is normally 400
μ
A, is reduced
as the output voltage nears AGND. T he full sink capability of
400
μ
A is maintained over the full output voltage range by tying
V
SS
to –5 V. T his is indicated in Figure 2.
500
0
10
300
100
2
200
0
400
8
6
4
V
OUT
– Volts
I
S
μ
A
V
SS
= –5V
V
SS
= 0V
V
DD
= +15V
T
A
= 25
°
C
Figure 2. Variation of I
SINK
with V
OUT
Settling-time for negative-going output signals approaching
AGND is similarly affected by V
SS
. Negative-going settling-time
for single supply operation is longer than for dual supply opera-
tion. Positive-going settling-time is not affected by V
SS
.
Additionally, the negative V
SS
gives more headroom to the out-
put amplifier which results in better zero code performance and
improved slew-rate at the output, than can be obtained in the
single supply mode.
DIGIT AL SE CT ION
T he AD7224 digital inputs are compatible with either T T L or
5 V CMOS levels. All logic inputs are static-protected MOS
gates with typical input currents of less than 1 nA. Internal in-
put protection is achieved by an on-chip distributed diode be-
tween DGND and each MOS gate. T o minimize power supply
currents, it is recommended that the digital input voltages be
driven as close to the supply rails (V
DD
and DGND) as practi-
cally possible.
INT E RFACE LOGIC INFORMAT ION
T able I shows the truth table for AD7224 operation. T he part
contains two registers, an input register and a DAC register.
CS
and
WR
control the loading of the input register while
LDAC
and
WR
control the transfer of information from the input regis-
ter to the DAC register. Only the data held in the DAC register
will determine the analog output of the converter.
All control signals are level-triggered and therefore either or
both registers may be made transparent; the input register by
keeping
CS
and
WR
“LOW”, the DAC register by keeping
LDAC
and
WR
“LOW”. Input data is latched on the rising
edge of
WR
.
T E RMINOLOGY
T OT AL UNADJUST E D E RROR
T otal Unadjusted Error is a comprehensive specification which
includes full-scale error, relative accuracy and zero code error.
Maximum output voltage is V
REF
– 1 LSB (ideal), where 1 LSB
(ideal) is V
REF
/256. T he LSB size will vary over the V
REF
range.
Hence the zero code error, relative to the LSB size, will increase
as V
REF
decreases. Accordingly, the total unadjusted error,
which includes the zero code error, will also vary in terms of
LSBs over the V
REF
range. As a result, total unadjusted error is
specified for a fixed reference voltage of +10 V.
RE LAT IVE ACCURACY
Relative Accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after al-
lowing for zero code error and full-scale error and is normally
expressed in LSBs or as a percentage of full-scale reading.
DIFFE RE NT IAL NONLINE ARIT Y
Differential Nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of
±
1 LSB max over
the operating temperature range ensures monotonicity.
DIGIT AL FE E DT HROUGH
Digital Feedthrough is the glitch impulse transferred to the out-
put due to a change in the digital input code. It is specified in
nV secs and is measured at V
REF
= 0 V.
FULL-SCALE E RROR
Full-Scale Error is defined as:
Measured Value – Zero Code Error – Ideal Value
CIRCUIT INFORMAT ION
D/A SE CT ION
T he AD7224 contains an 8-bit voltage-mode digital-to-analog
converter. T he output voltage from the converter has the same
polarity as the reference voltage, allowing single supply opera-
tion. A novel DAC switch pair arrangement on the AD7224 al-
lows a reference voltage range from +2 V to +12.5 V.
T he DAC consists of a highly stable, thin-film, R-2R ladder and
eight high speed NMOS single pole, double-throw switches.
T he simplified circuit diagram for this DAC is shown in
Figure 1.
V
OUT
R
R
R
2R
2R
2R
2R
2R
DB0
DB0
DB0
DB0
V
REF
AGND
SHOWN FOR ALL 1's ON DAC
Figure 1. D/A Simplified Circuit Diagram
T he input impedance at the V
REF
pin is code dependent and can
vary from 8 k
minimum to infinity. T he lowest input imped-
ance occurs when the DAC is loaded with the digital code
01010101. T herefore, it is important that the reference presents
a low output impedance under changing load conditions. T he
nodal capacitance at the reference terminals is also code depen-
dent and typically varies from 25 pF to 50 pF.
T he V
OUT
pin can be considered as a digitally programmable
voltage source with an output voltage of:
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7224BQ | LC2MOS 8-Bit DAC with Output Amplifiers |
| AD7224KN | ECONOLINE: REC2.2-S_DR/H1 - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- UL94V-0 Package Material- Continuous Short Circiut Protection- Internal SMD design- 100% Burned In- Efficiency to 75% |
| AD7224KP | ECONOLINE: REC2.2-S_DRW(Z)/H* - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- 4.5-9V, 9-18V, 18-36V, 36-72V Wide Input Range 2 : 1- UL94V-0 Package Material- Continuous Short Circiut Protection- Cost Effective- 100% Burned In- Efficiency to 84% |
| AD7224LN | LC2MOS 8-Bit DAC with Output Amplifiers |
| AD7224LP | LC2MOS 8-Bit DAC with Output Amplifiers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7224BQ | 制造商:Rochester Electronics LLC 功能描述:CMOS DAC IC - Bulk |
| AD7224CQ | 功能描述:IC DAC 8BIT W/AMP 18-CDIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時(shí)間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD7224KCWN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Digital-to-Analog Converter |
| AD7224KN | 功能描述:IC DAC 8BIT LC2MOS 18-DIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:47 系列:- 設(shè)置時(shí)間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:* |
| AD7224KNZ | 功能描述:IC DAC 8BIT LC2MOS 18-DIP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時(shí)間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。