參數資料
型號: AD7194BCPZ
廠商: Analog Devices Inc
文件頁數: 37/57頁
文件大?。?/td> 0K
描述: IC ADC 24BIT SPI 4.8K 32-LFCSP
產品培訓模塊: Weigh Scale Introduction
標準包裝: 1
位數: 24
采樣率(每秒): 4.8k
數據接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉換器數目: 1
電壓電源: 模擬和數字
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 32-WFQFN 裸露焊盤,CSP
供應商設備封裝: 32-LFCSP-WQ(5x5)
包裝: 管件
輸入數目和類型: 8 個差分,單極;8 個差分,雙極;16 個偽差分,單極;16 偽差分,雙極
產品目錄頁面: 777 (CN2011-ZH PDF)
其它名稱: AD7194BRUZ
AD7194BRUZ-ND
Data Sheet
AD7194
Rev. A | Page 41 of 56
The output data rate is 50 Hz when zero latency is disabled and
12.5 Hz when zero latency is enabled. Figure 34 shows the
frequency response of the sinc4 filter. The filter provides 50 Hz
±1 Hz and 60 Hz ± 1 Hz rejection of 82 dB minimum, assuming
a stable 4.92 MHz master clock.
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
25
50
75
100
125
150
FREQUENCY (Hz)
FI
L
T
E
R
G
AI
N
(
d
B)
08566-
033
Figure 34. Sinc4 Filter Response (FS[9:0] = 96, REJ60 = 1)
SINC3 FILTER (CHOP DISABLED)
A sinc3 filter can be used instead of the sinc4 filter. The filter is
selected using the SINC3 bit in the mode register. The sinc3
filter is selected when the SINC3 bit is set to 1.
This filter has good noise performance when operating with
output data rates up to 1 kHz. It has moderate settling time and
moderate 50 Hz/60 Hz (±1 Hz) rejection.
SINC3/SINC4
POST FILTER
MODULATOR
ADC
CHOP
08566-
034
Figure 35. Sinc3 Filter (Chop Disabled)
Sinc3 Output Data Rate and Settling Time
The output data rate (the rate at which conversions are available
on a single channel when the ADC is continuously converting)
is equal to
fADC = fCLK/(1024 × FS[9:0])
where:
fADC is the output data rate.
fCLK is the master clock (4.92 MHz nominal).
FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the
mode register.
The output data rate can be programmed from 4.7 Hz to
4800 Hz; that is, FS[9:0] can have a value from 1 to 1023.
The settling time is equal to
tSETTLE = 3/fADC
The 3 dB frequency is equal to
f3dB = 0.272 × fADC
Table 30 gives some examples of FS settings and the corres-
ponding output data rates and settling times.
Table 30. Examples of Output Data Rates and the
Corresponding Settling Time
FS[9:0]
Output Data Rate (Hz)
Settling Time (ms)
480
10
300
96
50
60
80
60
50
When a channel change occurs, the modulator and filter reset.
The complete settling time is allowed to generate the first
conversion after the channel change (see Figure 36). Subsequent
conversions on this channel are available at 1/fADC.
CHANNEL
CONVERSIONS
CHANNEL A
CH A
CH B
CHANNEL B
1/
fADC
08566-
035
Figure 36. Sinc3 Channel Change
When conversions are performed on a single channel and a step
change occurs, the ADC does not detect the change in analog
input. Therefore, it continues to output conversions at the
programmed output data rate. However, it is at least three
conversions later before the output data accurately reflects the
analog input. If the step change occurs while the ADC is
processing a conversion, the ADC takes four conversions after
the step change to generate a fully settled result.
1/
fADC
ANALOG
INPUT
ADC
OUTPUT
FULLY
SETTLED
08566-
036
Figure 37. Asynchronous Step Change in Analog Input
Sinc3 Zero Latency
Zero latency is enabled by setting the single bit (Bit 11) in the
mode register to 1. With zero latency, the complete settling time
is allowed for each conversion. Therefore, the conversion time
when converting on a single channel or when converting on
several channels is constant. The user does not need to consider
the effects of channel changes on the output data rate.
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