參數(shù)資料
型號(hào)： AD7156BCPZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 16/28頁(yè)
文件大?。?/td> 0K
描述： IC CDC 2CH 12BIT 1.8V 10LFCSP
標(biāo)準(zhǔn)包裝： 1
類型： 電容數(shù)字轉(zhuǎn)換器
分辨率（位）： 12 b
采樣率（每秒）： 100k
數(shù)據(jù)接口： 串行
電壓電源： 單電源
電源電壓： 1.8 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 10-WFDFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 10-LFCSP-WD（3x3）
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面： 781 (CN2011-ZH PDF)
其它名稱： AD7156BCPZ-REEL7DKR
AD7156
Rev. 0 | Page 23 of 28
If a repeated start condition is encountered after the address
pointer byte, all peripherals connected to the bus respond exactly
as outlined previously for a start condition; that is, a repeated
start condition is treated the same as a start condition. When a
master device issues a stop condition, it relinquishes control of
the bus, allowing another master device to take control of the
bus. Therefore, a master wanting to retain control of the bus
issues successive start conditions known as repeated start
conditions.
AD7156 RESET
To reset the AD7156 without having to reset the entire serial
bus, an explicit reset command is provided. This uses a particular
address pointer word as a command word to reset the part and
upload all default settings. The AD7156 does not respond to the
serial bus commands (do not acknowledge) during the default
values upload for approximately 2 ms.
The reset command address word is 0xBF.
GENERAL CALL
When a master issues a slave address consisting of seven 0s
with the eighth bit (R/W) set to 0, this is known as the general
call address. The general call address is for addressing every
device connected to the serial bus. The AD7156 acknowledges
this address and reads in the following data byte.
If the second byte is 0x06, the AD7156 is reset, completely
uploading all default values. The AD7156 does not respond
to the serial bus commands (do not acknowledge) during the
default values upload for approximately 2 ms.
The AD7156 does not acknowledge any other general call
commands.
1 – 7
89
8
9
89
P
S
START ADDR R/W ACK SUBADDRESS ACK
DATA
ACK
STOP
SDA
SCL
0
7
726
-05
0
Figure 40. Bus Data Transfer
DATA
A(S)
S SLAVE ADDR A(S)
SUB ADDR
A(S)
LSB = 0
LSB = 1
DATA
P
S SLAVE ADDR A(S)
SUB ADDR A(S) S SLAVE ADDR
A(S)
DATA
A(M)
DATA
P
WRITE
SEQUENCE
READ
SEQUENCE
A(S) = NO ACKNOWLEDGE BY SLAVE
A(M) = NO ACKNOWLEDGE BY MASTER
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
S = START BIT
P = STOP BIT
A(S)
A(M)
077
26
-05
1
Figure 41. Write and Read Sequences
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