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參數(shù)資料
| 型號： | AD7142ACPZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/73頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CAP-TO-DGTL CONV PROG 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 電容數(shù)字轉(zhuǎn)換器 |
| 分辨率（位）： | 16 b |
| 采樣率（每秒）： | 250k |
| 數(shù)據(jù)接口： | 串行 |
| 電壓電源： | 單電源 |
| 電源電壓： | 2.6 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 781 (CN2011-ZH PDF) |
| 其它名稱： | AD7142ACPZ-REELDKR |
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AD7142
Rev. A | Page 23 of 72
CD
C
O
U
T
P
U
T
CO
DE
S
t
SENSOR 1 INT
ASSERTED
1
2
3
4
5
6
STAGE_HIGH_THRESHOLD
(POST CALIBRATED
REGISTER VALUE)
05
70
2-
0
24
CHANGING ENVIRONMENTAL CONDITIONS
NOTES
1. INITIAL STAGE_OFFSET_HIGH REGISTER VALUE
2. POST CALIBRATED REGISTER STAGE_HIGH_THRESHOLD
3. POST CALIBRATED REGISTER STAGE_HIGH_THRESHOLD
4. INITIAL STAGE_LOW_THRESHOLD
5. POST CALIBRATED REGISTER STAGE_LOW_THRESHOLD
6. POST CALIBRATED REGISTER STAGE_LOW_THRESHOLD
CDC AMBIENT
VALUE DRIFTING
STAGE_LOW_THRESHOLD
(POST CALIBRATED
REGISTER VALUE)
SENSOR 2 INT
ASSERTED
Figure 35. Typical Sensor Behavior with Calibration Applied on the Data Path
SLOW FIFO
As shown in Figure 32, there are a number of FIFOs
implemented on the AD7142. These FIFOs are located in
Bank 3 of the on-chip memory. The slow FIFOs are used by the
on-chip logic to monitor the ambient capacitance level from
each sensor.
AVG_FP_SKIP and AVG_LP_SKIP
In Register 0x001, Bits[13:12] are the slow FIFO skip control for
full power mode, AVG_FP_SKIP. Bits[15:14] in the same
register are the slow FIFO skip control for low power mode,
AVG_LP_SKIP. These values determine which CDC samples
are not used (skipped) in the slow FIFO. Changing theses values
slows down or speeds up the rate at which the ambient
capacitance value tracks the measured capacitance value read by
the converter.
Slow FIFO update rate in full power mode = AVG_FP_SKIP ×
[(3 × Decimation Rate) × (SEQUENCE_STAGE_NUM +1) ×
(FF_SKIP_CNT +1) × 4 × 10-7]
Slow FIFO update rate in low power mode = (AVG_LP_SKIP +1) ×
[(3 × Decimation Rate) × (SEQUENCE_STAGE_NUM +1) ×
(FF_SKIP_CNT +1) × 4 × 10-7] / [(FF_SKIP_CNT +1 ) +
LP_CONV_DELAY]
The slow FIFO is used by the on-chip logic to track the ambient
capacitance value. The slow FIFO expects to receive samples
from the converter at a rate of 33 ms to 40 ms. AVG_FP_SKIP
and AVG_LP_SKIP are used to normalize the frequency of the
samples going into the FIFO, regardless of how many
conversion stages are in a sequence.
Determining the AVG_FP_SKIP and AVG_LP_SKIP value is
only required once during the initial setup of the capacitance
sensor interface. Recommended values for these settings when
using all 12 conversion stages on the AD7142 are:
AVG_FP_SKIP = 00 = skip 3 samples
AVG_LP_SKIP = 00 = skip 0 samples
SLOW_FILTER_UPDATE_LVL
The SLOW_FILTER_UPDATE_LVL controls whether the most
recent CDC measurement goes into the Slow FIFO (slow filter)
or not. The slow filter is updated when the difference between
the current CDC value and last value pushed into the slow FIFO
> SLOW_FILTER_UPDATE_LVL. This variable is in Ambient
Control Register 1, at Address 0x003.
Y
SENSITIVIT
THRESHOLD
POS
HIGH
OFFSET
STAGE
HIGH
OFFSET
STAGE
HIGH
OFFSET
STAGE
AMBIENT
SF
STAGE
THRESHOLD
HIGH
STAGE
_
16
4
_
4
_
×
+
=
Equation 1. On-Chip Logic Stage High Threshold Calculation
Y
SENSITIVIT
THRESHOLD
NEG
LOW
OFFSET
STAGE
LOW
OFFSET
STAGE
LOW
OFFSET
STAGE
AMBIENT
SF
STAGE
THRESHOLD
LOW
STAGE
_
16
4
_
4
_
×
+
=
Equation 2. On-Chip Logic Stage Low Threshold Calculation
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