參數(shù)資料
型號: AD712JR
廠商: Analog Devices Inc
文件頁數(shù): 6/20頁
文件大小: 0K
描述: IC OPAMP BIFET DUAL PREC 8SOIC
標(biāo)準(zhǔn)包裝: 98
放大器類型: J-FET
電路數(shù): 2
轉(zhuǎn)換速率: 20 V/µs
-3db帶寬: 4MHz
電流 - 輸入偏壓: 25pA
電壓 - 輸入偏移: 300µV
電流 - 電源: 5mA
電流 - 輸出 / 通道: 25mA
電壓 - 電源,單路/雙路(±): 9 V ~ 36 V,±4.5 V ~ 20 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SO
包裝: 管件
AD712
Rev. H | Page 14 of 20
APPLICATIONS INFORMATION
GUARDING
The low input bias current (15 pA) and low noise characteristics
of the AD712 BiFET op amp make it suitable for electrometer
applications such as photo diode preamplifiers and picoampere
current-to-voltage converters. The use of a guarding technique,
such as that shown in Figure 38, in printed circuit board (PCB)
layout and construction is critical to minimize leakage currents.
The guard ring is connected to a low impedance potential at the
same level as the inputs. High impedance signal lines should
not be extended for any unnecessary length on the PCB.
8
7
6
5
4
3
2
1
PDIP (N), CERDIP (Q),
AND SOIC (R) PACKAGES.
00
82
3-
03
8
Figure 38. Board Layout for Guarding Inputs
DAC CONVERTER APPLICATIONS
The AD712 is an excellent output amplifier for CMOS DACs. It can
be used to perform both 2-quadrant and 4-quadrant operations.
The output impedance of a DAC using an inverted R-2R ladder
approaches R for codes containing many 1s, and 3R for codes
containing a single 1. For codes containing all 0s, the output
impedance is infinite.
For example, the output resistance of the AD7545 modulates
between 11 kΩ and 33 kΩ. Therefore, with an 11 kΩ DAC
internal feedback resistance, the noise gain varies from 2 to 4/3.
This changing noise gain modulates the effect of the input offset
voltage of the amplifier, resulting in nonlinear DAC amplifier
performance.
The AD712K with guaranteed 700 μV offset voltage minimizes
this effect to achieve 12-bit performance.
Figure 39 and Figure 40 show the AD712 and AD7545 (12-bit
CMOS DAC) configured for unipolar binary (2-quadrant multi-
plication) or bipolar (4-quadrant multiplication) operation.
Capacitor C1 provides phase compensation to reduce overshoot
and ringing.
+15V
1/2
AD712
VIN
VREF
VDD
RFB
OUT1
AGND
AD7545
DGND
VOUTA
R2A*
DB11 TO DB0
0.1F
VDD
R1A*
1/2
AD712
VIN
VREF
VDD
RFB
OUT1
AGND
AD7545
DGND
VOUTB
R2B*
DB11 TO DB0
0.1F
–15V
R1B*
VDD
C1A
33pF
ANALOG
COMMON
*REFER TO
TABLE 3
GAIN
ADJUST
C1B
33pF
ANALOG
COMMON
GAIN
ADJUST
*REFER TO
TABLE 3
+
+
008
23-
039
Figure 39. Unipolar Binary Operation
R1 and R2 calibrate the zero offset and gain error of the DAC.
Specific values for these resistors depend upon the grade of
AD7545 and are listed in Table 3.
Table 3. Recommended Trim Resistor Values vs. Grades of
the AD7545 for VDD = 5 V
Trim
Resistor
JN/AQ
KN/BQ
LN
GLN
R1
500 Ω
200 Ω
100 Ω
20 Ω
R2
150 Ω
68 Ω
33 Ω
6.8 Ω
+15V
1/2
AD712
VIN
VREF
RFB
OUT1
AGND
AD7545
DGND
R2*
DATA INPUT
0.1F
VDD
R1*
1/2
AD712
VOUT
0.1F
–15V
12
DB11 TO DB0
R4
20k
1%
R5
20k
1%
R3
10k
1%
C1
33pF
ANALOG
COMMON
VDD
GAIN
ADJUST
*FOR VALUES OF
R1 AND R2 SEE TABLE 3
+
+
00
82
3-
04
0
Figure 40. Bipolar Operation
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