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參數(shù)資料
| 型號(hào)： | AD7010 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CMOS JDC DQPSK Baseband Transmit Port(CMOS 基帶傳輸口) |
| 中文描述： | 聯(lián)合紀(jì)律委員會(huì)DQPSK的CMOS基帶傳輸端口（的CMOS基帶傳輸口） |
| 文件頁數(shù)： | 3/8頁 |
| 文件大小： | 257K |
| 代理商： | AD7010 |
AD7010
REV. B
–3–
20k
20k
20pF
20pF
AD7010
ITx/QTx
40k
ITx / QTx
Figure 1. Analog Output Load Test Circuit
Q
I
MODULAR OUTPUT
DURING FTEST
Figure 2. Modulator State During FTEST
MASTER CLOCK TIMNG
Parameter
Limit at T
A
= –40
8
C to +85
8
C
Units
Description
t
1
t
2
t
3
300
100
100
ns min
ns min
ns min
MCLK Cycle T ime
MCLK High T ime
MCLK Low T ime
ABSOLUT E MAX IMUM RAT INGS*
(T
A
= +25
°
C unless otherwise noted)
V
DD
T x, V
DD
Rx to AGND . . . . . . . . . . . . . . . –0.3 V to +7 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V
Digital I/O Voltage to DGND . . . . . –0.3 V to V
DD
to + 0.3 V
Analog I/O Voltage to AGND . . . . . . . –0.3 V to V
DD
+ 0.3 V
Operating T emperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . –40
°
C to +85
°
C
Storage T emperature Range . . . . . . . . . . . . –65
°
C to +150
°
C
Junction T emperature . . . . . . . . . . . . . . . . . . . . . . . . +150
°
C
SSOP
θ
JA
T hermal Impedance . . . . . . . . . . . . . . . . +122
°
C/W
Lead T emperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215
°
C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220
°
C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
T able I.
MODE 1
MODE 2
Operation
0
0
1
0
1
X
Digital JDC Mode
FT EST
Factory T est, Reserved
WARNING!
ESD SENSITIVE DEVICE
C AUT ION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7010 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
(V
AA
= V
DD
= +5 V
6
10%; AGND = DGND = OV. All specifications are T
MN
to T
MAX
unless
otherwse noted.)
Figure 3. Master Clock (MCLK) Timing
Figure 4. Load Circuit for Digital Outputs
MCLK
t
2
t
1
t
3
TO OUTPUT
PIN
+2.1V
I
OH
C
L
100pF
1.6mA
200
μ
A
I
OL
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