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參數(shù)資料
| 型號： | AD7008 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | M83723 3C 3#16 SKT PLUG |
| 中文描述： | 的CMOS DDS調(diào)制器 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 505K |
| 代理商： | AD7008 |
REV. B
–6–
AD7008
AD7008
REGISTER
AND
CONTROL
LOGIC
32
12
20
32
12
PHASE
ACCUMULATOR
ACCUM RESET
SLEEP
AM ENABLE
PHASE
SUMMATION
12
SIN
COS
ROM
10
10
10
10
DAC
10
SIN/COS
SUMMATION
11 PIPELINE DELAYS
13 PIPELINE DELAYS
9:0 19:10
IOUT/
IOUT
14 PIPELINE DELAYS
Figure 7. AD7008 CMOS DDS Modulator (See Table I)
CS
(27)
D0-D15
(19-26, 8-15)
TC0-TC3
(32-35)
ACCUMULATOR
RESET
CLK
D Q
x
6
D Q
x
6
D Q
x
6
D Q
x
6
D
Q
x
6
PASS
1
0
x
6
CLK
LOAD (36)
FSEL (31)
D Q
D Q
D Q
CLK
RESET (38)
RESET SYNCHRONIZATION
TRANSFER CONTROL (TC) REGISTER
CLK
D Q
x
5
TC0
TC1
LOAD
TC3
TC2
D Q
TC3
TC2
0
1
2
3
4
S
E
0
1
2
3
2
3
4
0
1
D Q
x
20
E
FREQ 0
FREQ 1
FREQUENCY
REGISTERS
PHASE REGISTER
12
D Q
x
12
E
CLK
D Q
x
32
E
IQ MOD REGISTER
10
1
0
x
32
TO PHASE
SUMMATION
TO SIN/COS
SUMMATION
TO PHASE
ACCUMULATOR
CLK
CLK
CLK
32
32
TRANSFER DECODE
FSELECT
CLOCK (30)
x
5
D FLIP-FLOPS ARE MASTER SLAVE,
LATCHING DATA ON CLK RISING EDGE.
PASS FLIP-FLOPS ARE TRANSPARENT
WHEN THE CLOCK IS LOW.
CLK
1
0
x
24
WR
(16)
SCLK (41)
SDATA (42)
SLEEP (37)
15:0 23:8
15:8 7:0
7:0
23:0
D Q
x
32
32-BIT SERIAL
ASSEMBLY REGISTER
32-BIT PARALLEL
ASSEMBLY REGISTER
D Q
x
32
REGISTER
MUX
31:0
31:0
D Q
x
4
D Q
CLK
3:0
1
0
x
32
D Q
D1
D2
BUS MODE
SYNCHRO LOGIC
D0
D3
D Q
D Q
CLK
AM ENABLE
SLEEP
COMMAND REGISTER
CLK
CLK
CLK
31:8
D Q
x
32
E
5
6
Figure 8. AD7008 Register and Control Logic
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
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