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參數(shù)資料
| 型號(hào)： | AD698 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Universal LVDT Signal Conditioner |
| 中文描述： | 通用LVDT信號(hào)調(diào)理 |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大小： | 228K |
| 代理商： | AD698 |
AD698
REV. B
–7–
b. Full-scale core displacement from null, d
S
×
d = VT R and also equals the ratio A/B at mechanical full
scale. T he VT R should be converted to units of V/V.
For a full-scale displacement of d inches, voltage out of the
AD698 is computed as
V
OUT
= S
×
d
×
500
μ
A
×
R
2
V
OUT
is measured with respect to the signal reference,
Pin 21, shown in Figure 7.
Solving for R2,
R
2
=
V
OUT
S
×
d
×
500
μ
A
(1)
For V
OUT
=
±
10 V full-scale range (20 V span) and d =
±
0.1
inch full-scale displacement (0.2 inch span)
R
2
=
20
V
2.4
×
0.2
×
500
μ
A
=
83.3
k
V
OUT
as a function of displacement for the above example is
shown in Figure 10.
+10
+0.1d (INCHES)
–0.1
–10
V
OUT
(VOLTS)
Figure 10. V
OUT
(
±
10 V Full Scale) vs. Core Displace-
ment (
±
0.1 Inch)
E . Optional Offset of Output Voltage Swing
9. Selections of R3 and R4 permit a positive or negative output
voltage offset adjustment.
For no offset adjustment R3 and R4 should be open circuit.
T o design a circuit producing a 0 V to +10 V output for a
displacement of +0.1 inch, set V
OUT
to +10 V, d = 0.2 inch
and solve Equation (1) for R2.
V
OS
=
1.2
V
×
R
2
×
1
R
3
+
2
k
±
1
R
4
+
2
k
(2)
+5
+0.1d (INCHES)
–0.1
–5
V
OUT
(VOLTS)
Figure 11. V
OUT
(
±
5 V Full Scale) vs. Core Displacement
(
±
0.1 Inch)
T his will produce a response shown in Figure 11.
In Equation (2) set V
OS
= 5 V and solve for R3 and R4. Since a
positive offset is desired, let R4 be open circuit. Rearranging
Equation (2) and solving for R3
R
3
=
1.2
×
R
2
V
OS
±2
k
=
7.02
k
Multiply the primary excitation voltage by the VT R to get
the expected secondary voltage at mechanical full scale. For
example, for an LVDT with a sensitivity of 2.4 mV/V/mil and
a full scale of
±
0.1 inch, the VT R = 0.0024 V/V/Mil
×
100
mil = 0.24. Assuming the maximum excitation of 3.5 V rms,
the maximum secondary voltage will be 3.5 V rms
×
0.24 =
0.84 V rms, which is in the acceptable range.
Conversely the VT R may be measured explicitly. With the
LVDT energized at its typical drive level V
PRI
, as indicated
by the manufacturer, set the core displacement to its me-
chanical full-scale position and measure the output V
SEC
of
the secondary. Compute the LVDT voltage transformation
ratio, VT R. VT R = V
SEC
//VPRI. For the E100, V
SEC
= 0.72 V
for V
PRI
= 3 V. VT R = 0.24.
For situations where LVDT sensitivity is low, or the me-
chanical FS is a small fraction of the total stroke length, an
input excitation of more than 3.5 V rms may be needed. In
this case a voltage divider network may be placed across the
LVDT primary to provide smaller voltage for the +BIN and
–BIN input. If, for example, a network was added to divide
the B Channel input by 1/2, then the VT R should also be re-
duced by 1/2 for the purpose of component selection.
Check the power supply voltages by verifying that the peak
values of V
A
and V
B
are at least 2.5 volts less than the volt-
ages at +V
S
and –V
S
.
6. Referring to Figure 9, for V
S
=
±
15 V, select the value of the
amplitude determining component R1 as shown by the curve
in Figure 9.
30
15
0
0.01
0.1
1k
100
10
1
5
10
20
25
V rms
R1 – k
V
E
–
Figure 9. Excitation Voltage V
EXC
vs. R1
7. C2, C3 and C4 are a function of the desired bandwidth of
the AD698 position measurement subsystem. T hey should
be nominally equal values.
C
2 =
C
3 =
C
4 = 10
–4
Farad Hz/f
5UBSYSTEM
(
Hz
)
If the desired system bandwidth is 250 Hz, then
C
2 =
C
3 =
C
4 = 10
-4
F
arad Hz
/250
Hz
= 0.4
μ
F
See Figures 14, 15 and 16 for more information about
AD698 bandwidth and phase characterization.
D. Set the Full-Scale Output Voltage
8. T o compute R2, which sets the AD698 gain or full-scale
output range, several pieces of information are needed:
a. LVDT sensitivity, S
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