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| 型號： | AD670JN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Low Cost Signal Conditioning 8-Bit ADC |
| 中文描述： | 2-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDIP20 |
| 封裝： | PLASTIC, DIP-20 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大小： | 364K |
| 代理商： | AD670JN |
AD670
REV. A
–7–
Table III. AD670 TIMING SPECIFICATIONS
@ +25
8
C
Typ
Symbol
Parameter
Min
Max
Units
WRITE/CONVERT START MODE
t
W
Write/Start Pulse Width
t
DS
Input Data Setup Time
t
DH
Input Data Hold
t
RWC
Read/Write Setup Before Control
t
DC
Delay to Convert Start
t
C
Conversion Time
300
200
10
0
ns
ns
ns
ns
ns
μ
s
700
10
READ MODE
t
R
t
SD
t
TD
t
DH
t
DT
t
RT
Read Time
Delay from Status Low to Data Read
Bus Access Time
Data Hold Time
Output Float Delay
R/
W
before
CE
or
CS
low
250
ns
ns
ns
ns
ns
ns
250
250
200
25
150
0
Boldface indicates parameters tested 100% unless otherwise noted. See Specifications page for explanation.
6b. Bipolar
6c. Full Scale (Unipolar)
Figure 6. Transfer Curves
CONTROL AND TIMING OF THE AD670
Control Logic
The AD670 contains on-chip logic to provide conversion and
data read operations from signals commonly available in micro-
processor systems. Figure 7 shows the internal logic circuitry of
the AD670. The control signals,
CE
,
CS
, and R/
W
control the
operation of the converter. The read or write function is deter-
mined by R/
W
when both
CS
and
CE
are low as shown in
Table II. If all three control inputs are held low longer than the
conversion time, the device will continuously convert until one
input,
CE
,
CS
, or R/
W
is brought high. The relative timing of
these signals is discussed later in this section.
Figure 7. Control Logic Block Diagram
Table II. AD670 Control Signal Truth Table
R/
W
CS
CE
OPERATION
0
1
X
X
0
0
X
1
0
0
1
X
WRITE/CONVERT
READ
NONE
NONE
Timing
The AD670 is easily interfaced to a variety of microprocessors
and other digital systems. The following discussion of the timing
requirements of the AD670 control signals will provide the de-
signer with useful insight into the operation of the device.
Write/Convert Start Cycle
Figure 8 shows a complete timing diagram for the write/convert
start cycle.
CS
(chip select) and
CE
(chip enable) are active low
and are interchangeable signals. Both
CS
and
CE
must be low
for the converter to read or start a conversion. The minimum
pulse width, t
W
, on either
CS
or
CE
is 300 ns to start a
conversion.
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