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參數(shù)資料
| 型號(hào)： | AD669SQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Monolithic 16-Bit DACPORT |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 10 us SETTLING TIME, 16-BIT DAC, CDIP28 |
| 封裝： | CERDIP-28 |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 460K |
| 代理商： | AD669SQ |
AD669
REV. A
–3–
TIMING CHARACTERISTICS
V
CC
= +15 V, V
EE
= –15 V, V
LL
= +5 V, V
HI
= 2.4 V, V
LO
= 0.4 V
Limit
–40
8
C to
+85
8
C
Limit
–55
8
C to
+125
8
C
Limit
+25
8
C
Parameter
Units
(Figure la)
t
CS
t
LI
t
DS
t
DH
t
LH
t
LW
40
40
30
10
90
40
50
50
35
10
110
45
55
55
40
15
120
45
ns min
ns min
ns min
ns min
ns min
ns min
(Figure lb)
t
LOW
t
HIGH
t
DS
t
DH
130
40
120
10
150
45
140
10
165
45
150
15
ns min
ns min
ns min
ns min
Specifications subject to change without notice.
Specifications in
boldface
are tested on all production units at final electrical
test. Results from those tests are used to calculate outgoing quality levels. All
min and max specifications are guaranteed. Those shown in boldface are tested
on all production units.
AC PERFORMANCE CHARACTERISTICS
Ratio, these characteristics are included for design guidance only and are not subject to test. THD+N and SNR are 100% tested.
T
MIN
≤
T
A
≤
T
MAX
, V
CC
= +15 V, V
EE
= –15 V, V
LL
= +5 V except where noted.)
Parameter
Limit
Units
Test Conditions/Comments
Output Settling Time
(Time to
±
0.0008% FS
with 2 k
, 1000 pF Load)
13
8
10
6
8
2.5
μ
s max
μ
s typ
μ
s typ
μ
s typ
μ
s typ
μ
s typ
20 V Step, T
A
= +25
°
C
20 V Step, T
A
= +25
°
C
20 V Step, T
MIN
≤
T
A
≤
T
MAX
10 V Step, T
A
= +25
°
C
10 V Step, T
MIN
≤
T
A
≤
T
MAX
1 LSB Step, T
MIN
≤
T
A
≤
T
MAX
Total Harmonic Distortion + Noise
A, B, S Grade
A, B, S Grade
A, B, S Grade
0.009
0.07
7.0
% max
% max
% max
0 dB, 1001 Hz; Sample Rate = 100 kHz; T
A
= +25
°
C
–20 dB, 1001 Hz; Sample Rate = 100 kHz; T
A
= +25
°
C
–60 dB, 1001 Hz; Sample Rate = 100 kHz; T
A
= +25
°
C
Signal-to-Noise Ratio
83
dB min
T
A
= +25
°
C
Digital-to-Analog Glitch Impulse
15
nV-s typ
DAC Alternately Loaded with 8000H and 7FFFH
Digital Feedthrough
2
nV-s typ
DAC Alternately Loaded with 0000H and FFFFH;
CS
High
Output Noise Voltage
Density (1 kHz – 1 MHz)
120
nV/
√
Hz
typ
Measured at V
OUT
, 20 V Span; Excludes Reference
Reference Noise
125
nV/
√
Hz
typ
Measured at REF OUT
Specifications subject to change without notice.
Specifications in
boldface are
tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and
max specifications are guaranteed. Those shown in boldface are tested on all production units.
(With the exception of Total Harmonic Distortion + Noise and Signal-to-Noise
DATA
LDAC
t
DS
t
DH
CS
t
LW
t
LH
L1
t
CS
t
L1
Figure 1a. AD669 Level Triggered Timing Diagram
DATA
t
DS
t
DH
CS
AND/OR
L1
, LDAC
TIE
CS
AND/OR
L1
TO GROUND OR TOGETHER WITH LDAC
t
LOW
t
HIGH
Figure 1b. AD669 Edge Triggered Timing Diagram
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