參數(shù)資料
型號(hào)： AD6650BBC1
廠商： Analog Devices, Inc.
英文描述： Diversity IF to Baseband GSM/EDGE Narrowband Receiver
中文描述： 多樣性IF到基帶的GSM / EDGE窄帶接收器
文件頁(yè)數(shù)： 10/28頁(yè)
文件大小： 594K
代理商： AD6650BBC1
Preliminary Technical Data
TIMING DIAGRAMS
AD6650
REV. PrJ 02/27/2003
10
SYNC
CLK
t
SS
t
HS
Figure x. SYNC Timing Inputs
TIMING DIAGRAMS – INM Microport Mode
t
SAM
/RD (/DS)
/WR (RW)
/CS
A[2:0]
D[7:0]
RDY
(/DTACK)
Valid Address
Valid Data
t
SAM
t
HAM
t
HAM
t
DRDY
t
HWR
t
ACC
Notes:
1. t
ACC
Access time depends on the Address accessed. Access time is measured from FE of /WR to RE of RDY.
t
ACC
requires a maximum of 9 CLK periods
t
SC
t
HC
CLK
Figure 16. INM Microport Write Timing Requirements.
t
SAM
/RD (/DS)
/WR (RW)
/CS
A[2:0]
D[7:0]
RDY
(/DTACK)
Valid Address
t
ZD
t
DD
t
DRDY
t
ZD
t
ACC
Valid Data
t
HA
Notes:
1. t
ACC
Access time depends on the Address accessed. Access time is measured from FE of /WR to RE of RDY.
t
ACC
requires a maximum of 13 CLK periods and applies to A[2:0]=7,6,5,3,2,1
t
SC
t
HC
CLK
Figure 17. INM Microport Read Timing Requirements.
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