參數(shù)資料
型號(hào)： AD6623
廠商： Analog Devices, Inc.
英文描述： 4-Channel, 104 MSPS Digital Transmit Signal Processor TSP
中文描述： 4通道，104 MSPS的數(shù)字傳輸信號(hào)處理器判刑
文件頁數(shù)： 12/40頁
文件大?。?/td> 381K
代理商： AD6623
REV. 0
AD6623
–12–
128 PIN FUNCTION DESCRIPTIONS
Pin Number
Mnemonic
Type
Description
1, 3–5, 9, 19–21, 31, 32, 34–36, 38, 39,
42, 52–54, 64–65, 68, 72, 83–85, 95, 96,
98, 99, 102, 103, 116, 128
2
29, 28, 27, 25, 24, 23, 22, 18, 17, 16, 15,
13, 12, 11, 10, 8, 7, 6
47, 59, 66, 104, 127
14, 26, 41, 78, 90, 110, 122
30
GND
OEN
1
P
I
Ground Connection
Active High Output Enable Pin
OUT[17:0]
VDD
VDDIO
QOUT
O/T
P
P
O/T
Parallel Output Data
2.5 V Supply
3.3 V Supply
When HIGH indicates Q Output Data
(Complex Output Mode)
Bidirectional Microport Data
INM Mode: Read Signal, MNM Mode: Data Strobe Signal
33, 37, 40, 43, 44, 45, 46, 48
49
50
D[7:0]
DS
(
RD
)
DTACK
(RDY)
I/O/T
I
O
Acknowledgment of a Completed Transaction (Signals when
μ
P Port Is Ready for an Access) Open Drain, Must Be
Pulled Up Externally
Active HIGH Read, Active Low Write
Sets Microport Mode: MODE = 1, MNM Mode; MODE = 0,
INM Mode
Microport Address Bus
Chip Select, Active low enable for
μ
P Access
Active Low Reset Pin
SYNC Signal for Synchronizing Multiple AD6623s
SYNC Signal for Synchronizing Multiple AD6623s
Input Clock
SYNC Signal for Synchronizing Multiple AD6623s
When HIGH indicates Q input data (Complex Input Mode)
Wideband Input/Output Data (Allows Cascade of Multiple
AD6623 Chips In a System)
SYNC Signal for Synchronizing Multiple AD6623s
Test Reset Pin
Test Clock Input
Serial Data Frame Input—Channel A
Test Mode Select
Test Data Output
Test Data Input
Bidirectional Serial Clock—Channel A
Serial Data Frame Sync Output—Channel A
Serial Data Input—Channel A
Bidirectional Serial Clock—Channel B
Serial Data Frame Sync Output—Channel B
Serial Data Frame Input —Channel B
Serial Data Frame Input—Channel C
Serial Data Input—Channel B
Bidirectional Serial Clock—Channel C
Serial Data Frame Sync Output—Channel C
Serial Data Input—Channel C
Bidirectional Serial Clock—Channel D
Serial Data Frame Sync Outpu—Channel D
Serial Data Input—Channel D
Serial Data Frame Input—Channel D
51
55
RW (
WR
)
MODE
I
I
56, 57, 58
60
61
62
63
67
69
70
71, 74–77, 79–82, 86–89, 91–94, 97
A[2:0]
CS
RESET
2
SYNC0
1
SYNC1
1
CLK
1
SYNC2
1
QIN
1
INOUT[17:0]
1
I
I
I
I
I
I
I
I
I/O
73
100
101
105
106
107
108
109
111
112
113
114
115
117
118
119
120
121
123
124
125
126
SYNC3
1
TRST
2
TCK
1
SDFIA
TMS
2
TDO
TDI
1
SCLKA
SDFOA
SDINA
1
SCLKB
SDFOB
SDFIB
SDFIC
SDINB
1
SCLKC
SDFOC
SDINC
1
SCLKD
SDFOD
SDIND
1
SDFID
I
I
I
I
I
O
I
I/O
O
I
I/O
O
I
I
I
I/O
O
I
I/O
O
I
I
NOTES
1
Pins with a Pull-Down resistor of nominal 70 k
.
2
Pins with a Pull-Up resistor of nominal 70 k
.
相關(guān)PDF資料
PDF描述
AD6623ABC 4-Channel, 104 MSPS Digital Transmit Signal Processor TSP
AD6623AS 4-Channel, 104 MSPS Digital Transmit Signal Processor TSP
AD6623PCB 4-Channel, 104 MSPS Digital Transmit Signal Processor TSP
AD6624AS Four-Channel, 80 MSPS Digital Receive Signal Processor (RSP)
AD6624A Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD6623ABC 制造商:Analog Devices 功能描述:Signal Processor 196-Pin CSP-BGA 制造商:Rochester Electronics LLC 功能描述:4 CHANNEL, 104 MSPS DIGITAL TSP - Bulk
AD6623ABCZ 制造商:Analog Devices 功能描述:Signal Processor 196-Pin CSP-BGA
AD6623AS 制造商:Analog Devices 功能描述:Signal Processor 128-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:4 CHANNEL, 104 MSPS DIGITAL TSP - Bulk
AD6623ASZ 功能描述:IC TSP 4CHAN 104MSPS 128MQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1
AD6623BC/PCB 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, 104 MSPS Digital Transmit Signal Processor TSP
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