- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373890 > AD6622AS (ANALOG DEVICES INC) Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP PDF資料下載
參數(shù)資料
| 型號： | AD6622AS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP128 |
| 封裝： | METRIC, QFP-128 |
| 文件頁數(shù)： | 4/28頁 |
| 文件大?。?/td> | 242K |
| 代理商： | AD6622AS |
第1頁第2頁第3頁當(dāng)前第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
AD6622
–4–
REV. 0
Test
Level
AD6622AS
Typ
Name
Parameter (Conditions)
Temp
Min
Max
Unit
MICROPROCESSOR PORT, MODE MNM (MODE = 1)
MODE MNM Write Timing
:
t
HDS
t
HRW
t
SAM
t
HAM
t
DDTACK
t
ACC
FAST
t
ACC
MEDIUM
t
ACC
SLOW
MODE MNM Read Timing
:
t
SAM
t
HA
t
ZD
t
DD
t
DDTACK
t
ACC
FAST
t
ACC
MEDIUM
t
ACC
SLOW
DS
(
RD
) to
DTACK
(RDY) Hold Time
R/
W
(
WR
) to
DTACK
(RDY) Hold Time
Address/Data to R/
W
(
WR
) Setup Time
Address/Data to R/
W
(
WR
) Hold Time
DS
(
RD
) to
DTACK
(RDY) Delay
R/
W
(
WR
) to
DTACK
(RDY) Low Delay
R/
W
(
WR
) to
DTACK
(RDY) Low Delay
R/
W
(
WR
) to
DTACK
(RDY) Low Delay
Full
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
IV
IV
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
1
×
t
CLK
3
×
t
CLK
4
×
t
CLK
5
×
t
CLK
2
×
t
CLK
3
×
t
CLK
4
×
t
CLK
Address to
DS
(
RD
) Setup Time
Address to Data Hold Time
Data Three-State Delay
DTACK
(RDY) to Data Delay
DS
(
RD
) to
DTACK
(RDY) Delay
DS
(
RD
) to
DTACK
(RDY) Low Delay
DS
(
RD
) to
DTACK
(RDY) Low Delay
DS
(
RD
) to
DTACK
(RDY) Low Delay
Full
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
IV
IV
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
t
CLK
– 10
1
t
CLK
3
×
t
CLK
4
×
t
CLK
5
×
t
CLK
2
×
t
CLK
3
×
t
CLK
4
×
t
CLK
NOTES
1
All Timing Specifications valid over VDD range of 2.4 V to 3.3 V.
Specifications subject to change without notice.
CLK
OUT[17:0],
QOUT
t
CLK
t
CLKL
t
CLKH
t
ZO
t
HO
t
ZO
OEN
t
SO
Figure 1. Parallel Output Switching Characteristics
CLK
SCLK
SDFS
SDI
CLKn
DATAn
t
DSCLK
t
DSDFS
t
DSDFS
t
SSI
t
HSI
Figure 2. Serial Port Switching Characteristics
CLK
IN[17:0],
QIN
t
SI
t
HI
Figure 3. Wideband Input Timing
SYNC
CLK
t
SS
t
HS
Figure 4. SYNC Timing Inputs
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD6622PCB | Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6622S | Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6622 | Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6623 | 4-Channel, 104 MSPS Digital Transmit Signal Processor TSP |
| AD6623ABC | 4-Channel, 104 MSPS Digital Transmit Signal Processor TSP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD6622PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6622S | 制造商:AD 制造商全稱:Analog Devices 功能描述:Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6622S/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6623 | 制造商:Analog Devices 功能描述: |
| AD6623ABC | 制造商:Analog Devices 功能描述:Signal Processor 196-Pin CSP-BGA 制造商:Rochester Electronics LLC 功能描述:4 CHANNEL, 104 MSPS DIGITAL TSP - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。