參數(shù)資料
型號： AD6620AS
廠商： ANALOG DEVICES INC
元件分類： 微控制器/微處理器
英文描述： 65 MSPS Digital Receive Signal Processor
中文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PQFP80
封裝： PLASTIC, QFP-80
文件頁數(shù)： 39/43頁
文件大?。?/td> 354K
代理商： AD6620AS
AD6620
–39–
REV. 0
Software for Single Channel Real Operation
When interfacing Analog Device’s SHARC DSP, the following
code fragments can be used to configure the SHARC. The first
example shows how to configure the registers for use with a
single channel application. The first segment of code defines the
memory for use with the multichannel serial port data. The
second segment of code sets up the serial port for receiving data
only. It could have just as easily been set up for bidirectional
data by properly setting the MTCSI register. The final two code
segments are used when a serial port interrupt occurs. When the
SHARC detects completion of the serial port frame, an inter-
rupt is generated and the final code segment is executed. The
comments in that section show where user code should be in-
serted. The SHARC takes care of moving the serial port buffers
data directly to data memory as shown.
/* —————————————————————————————*/
/* multi-channel register setup */
.SEGMENT/DM dm_data;
.VAR fm_demod_data[2];
sample */
/* Array for receiving 1 real and imag
.VAR fm_demod_tcb[8] = 0, 0, 0, 0, fm_demod_data+7, 2, 1,
fm_demod_data;
/* Transfer Control Block for reception of fm data */
/* —————————————————————————————*/
/* —————————————————————————————*/
/* Subroutine to setup sport1 for use with the AD6620 */
setup_sport1:
r0 = 0;
dm(MTCS1) = r0;
/* multi-channel enable setup */
/* do not transmit on any channels */
r0 = 0;
dm(MTCCS1) = r0;
dm(MRCCS1) = r0;
/* Compand Setup */
/* no companding on transmit */
/* no companding on receive */
r0 = 0x00100000;
dm(STCTL1) = r0;
/* Setup sport 1 transmit control register */
/* mfd = 1 */
r0 = 0x038c20f2;
dm(SRCTL1) = r0;
/* Setup sport 1 receive control register */
/* slen = 15, sden & schen enabled */
/* sign extend, external SCLK+RFS */
r0 = fm_demod_tcb + 7; /* TCB address */
dm(CP1) = r0;
/* Kickoff DMA chain */
rts (db);
bit set imask SPR1I;
nop;
/* RETURN */
/* enable sport1 receive interrupt */
/* —————————————————————————————*/
spr1_svc:
jump spr1_asserted;
RTI;
RTI;
RTI;
/* —————————————————————————————*/
/* —————————————————————————————*/
/* Process received data here. Data samples located in fm_demod_data
and fm_demod_data+1
spr1_asserted:
push sts;
/* Push the status stack */
/* Use secondary set of DAGs and Register file */
bit set mode1 SRD1H | SRD2L | SRRFH | SRRFL;
nop;
/* Insert code here to process I and Q data. The DSP serial port handler
has placed the samples in fm_demod_data and fm_demod_data+1 */
pop sts;
rti (db);
/* Pop the status stack */
/* Switch back to primary set of DAGs and Register file */
bit clr mode1 SRD1H | SRD2L | SRRFH | SRRFL;
nop;
.ENDSEG;
/*—————————————————————————————*/
Software for Diversity Channel Real Operation
The code for interfacing to Diversity Channel Real mode is very
similar to that of single channel. The only difference being the
number of channels allocated on the TDM chain. This process
can easily be extended for any number of TDM channels as
long as there is sufficient time in the frame to completely trans-
mit the data. This procedure works with the appended data as
well as serially cascaded devices. The code below demonstrates
setup and operation in diversity channel mode.
/
*—————————————————————————————*/
.SEGMENT/DM dm_data;
/* multi-channel register setup */
.VAR fm_demod_data[4];
sample from each channel */
/* Array for receiving 2 real and imag
.VAR fm_demod_tcb[8] = 0, 0, 0, 0, 0, 4, 1, fm_demod_data;
/* Transfer Control Block for reception of fm data */
/* —————————————————————————————*/
/*—————————————————————————————*/
setup_sport1:
r0 = 0;
/* multi-channel enable setup */
dm(MTCS1) = r0;
/* do not transmit on any channels */
r0 = 0;
dm(MTCCS1) = r0;
dm(MRCCS1) = r0;
/* Compand Setup */
/* no companding on transmit */
/* no companding on receive */
r0 = 0x00100000;
dm(STCTL1) = r0;
/* Setup sport 1 transmit control register */
/* mfd = 1 */
r0 = 0x038c00f2;
dm(SRCTL1) = r0;
/* Setup sport 1 receive control register */
/* slen = 15, sden & schen enabled */
/* sign extend, external SCLK+RFS */
r0 = fm_demod_tcb + 7; /* TCB address */
dm(fm_demod_tcb + 4) = r0;
dm(CP1) = r0;
/* TCB point back to itself */
/* Kickoff DMA chain */
rts (db)
bit set imask SPR1I;
bit set imask CB15I;
interrupt for buffers full */
/*—————————————————————————————*/
/*—————————————————————————————*/
spr1_svc:
jump spr1_asserted;
RTI;
RTI;
RTI;
/* RETURN */
/* enable sport1 receive interrupt */
/* Enable circular buffer 15 wrap
相關PDF資料
PDF描述
AD6620S 65 MSPS Digital Receive Signal Processor
AD6620 65 MSPS Digital Receive Signal Processor(采樣速率65MSPS的數(shù)字接收信號處理器)
AD6622AS Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP
AD6622PCB Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP
AD6622S Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP
相關代理商/技術參數(shù)
參數(shù)描述
AD6620AS-REEL 制造商:Analog Devices 功能描述:Signal Processor 80-Pin PQFP T/R
AD6620ASZ 功能描述:IC DGTL RCVR DUAL 67MSPS 80-PQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產品:NXP - I2C Interface 標準包裝:1 系列:- 應用:2 通道 I²C 多路復用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1
AD6620ASZ-REEL 功能描述:IC DGTL RCVR DUAL 67MSPS 80-PQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產品:NXP - I2C Interface 標準包裝:1 系列:- 應用:2 通道 I²C 多路復用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1
AD6620PCB 制造商:AD 制造商全稱:Analog Devices 功能描述:65 MSPS Digital Receive Signal Processor
AD6620S 制造商:AD 制造商全稱:Analog Devices 功能描述:65 MSPS Digital Receive Signal Processor
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