參數(shù)資料
型號(hào)： AD652SQ
廠商： Analog Devices Inc
文件頁數(shù)： 20/28頁
文件大?。?/td> 779K
描述： IC V-F CONV SYNCH MONO 5V 16CDIP
標(biāo)準(zhǔn)包裝： 1
類型： 電壓至頻率
頻率 - 最大： 2MHz
全量程： ±25ppm/°C
線性： ±0.005%
安裝類型： 通孔
封裝/外殼： 16-CDIP（0.300"，7.62mm）
供應(yīng)商設(shè)備封裝： 16-CDIP
包裝： 管件
AD652
 
Rev. C | Page 20 of 28
SVFC Demultiplexer
The demultiplexer needed to separate the combined signals is
shown in Figure 30. A phase-locked loop drives another 4-phase
clock chip to lock onto the reconstructed clock signal. The sync
pulses are distinguished from the data pulses by their shorter
duration. Each falling edge on the multiplex input signal
triggers the one-shot; at the end of this one-shot pulse, the
multiplex input signal is sampled by a D-type flip-flop. If the
signal is high, the pulse was short (a sync pulse) and the
Q
output of the D-flop goes low. The D-flop is cleared a short time
(two gate delays) later, and the clock is reconstructed as a
stream of short, low-going pulses. If the multiplex input is a data
pulse, then the signal will still be low and no pulse will appear at
the reconstructed clock output when the D-flop samples at the
end of the one-shot period. See Figure 29.
If it is desired to recover the individual frequency signals, the
multiplex input is sampled with a D-flop at the appropriate
time, as determined by the rising edge of the various phases
generated by the clock chip. These frequency signals can be
counted as a ratio relative to the reconstructed clock, so it is not
even necessary for the transmitter to be crystal-controlled as
shown in Figure 30.
?SPAN class="pst AD652SQ_2632819_6">1
?SPAN class="pst AD652SQ_2632819_6">1
SYNC
?SPAN class="pst AD652SQ_2632819_6">2
?SPAN class="pst AD652SQ_2632819_6">3
DATA
?SPAN class="pst AD652SQ_2632819_6">4
?SPAN class="pst AD652SQ_2632819_6">2
?SPAN class="pst AD652SQ_2632819_6">3
?SPAN class="pst AD652SQ_2632819_6">4
1MULTIPLEX
OUTPUT
 
Figure 28. Multiplexer Waveforms
MULTIPLEX
INPUT
ONE SHOT
RECONSTRUCTED
CLOCK
?SPAN class="pst AD652SQ_2632819_6">1
(PHASE LOCKED TO
RECONSTRUCTED
CLOCK)
 
Figure 29. Demultiplexer Waveforms
14
13
5
4
10
4
2
11
8
9
0.1?/SPAN>F
PHASE LOCK LOOP
MC4044
3
1
3.01k&
719&
1k&
+5V
+5V
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
?SPAN class="pst AD652SQ_2632819_6">4
?SPAN class="pst AD652SQ_2632819_6">3
?SPAN class="pst AD652SQ_2632819_6">1
+5V
?SPAN class="pst AD652SQ_2632819_6">2
TANK 1
TIM 9904A
4 PHASE CLOCK
TANK 2    XTAL 2
XTAL 1
FFQ
OSCIN
FFD
OSCOUT
?SPAN class="pst AD652SQ_2632819_6">3
V
DD
?SPAN class="pst AD652SQ_2632819_6">4
?SPAN class="pst AD652SQ_2632819_6">1
?SPAN class="pst AD652SQ_2632819_6">2
GND 1
GND 2
V
CC
?SPAN class="pst AD652SQ_2632819_6">1 TTL
?SPAN class="pst AD652SQ_2632819_6">2 TTL
?SPAN class="pst AD652SQ_2632819_6">3 TTL
?SPAN class="pst AD652SQ_2632819_6">4 TTL
130&
150&
3
16
15
11
6
8
9
7
2
4
5
+5V
50pF
VCO
'LS629
390pF
'00
'00
CLEAR
Q
CLOCK
D  1/2 '74
RECONSTRUCTED
CLOCK OUTPUT
MPX
INPUT
1
14
2
13
3
12
4
11
5
10
6
9
7
8
Q Q
ONE SHOT
'121
GND
NC
R
INT
C
EXT
R
EXT
/C
EXT
NC
NC
V
CC
Q
+5V
A2
A1
NC
2k&
50pF
+5V
Q
D
CLOCK
Q
f2
?SPAN class="pst AD652SQ_2632819_6">2
'74 (1/2)
D
CLOCK
Q
f3
RECONSTRUCTED
FREQUENCY OUTPUTS
?SPAN class="pst AD652SQ_2632819_6">3
'74 (1/2)
D
CLOCK
Q
f4
?SPAN class="pst AD652SQ_2632819_6">4
'74 (1/2)
NC = NO CONNECT
 
Figure 30. SVFC Demultiplexers
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD652SQ/883B 功能描述:電壓頻率轉(zhuǎn)換及頻率電壓轉(zhuǎn)換 IC - SYNC V/F CONVERTER RoHS:否 制造商:Texas Instruments 全標(biāo)度頻率:4000 KHz 線性誤差:+/- 1 % FSR 電源電壓-最大: 電源電壓-最小: 最大工作溫度:+ 85 C 最小工作溫度:- 25 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-14 封裝:Tube
AD652SQ/883B2 制造商:AD 制造商全稱:Analog Devices 功能描述:Monolithic Synchronous Voltage-to-Frequency Converter
AD652SQ2 制造商:AD 制造商全稱:Analog Devices 功能描述:Monolithic Synchronous Voltage-to-Frequency Converter
AD652SQ883B2 制造商:AD 制造商全稱:Analog Devices 功能描述:Monolithic Synchronous Voltage-to-Frequency Converter
AD652SW 制造商:AD 制造商全稱:Analog Devices 功能描述:Monolithic Synchronous Voltage-to-Frequency Converter
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