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參數(shù)資料
| 型號(hào)： | AD648JNZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 10/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP BIFET 1MHZ DUAL LP 8DIP |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 放大器類型： | J-FET |
| 電路數(shù)： | 2 |
| 轉(zhuǎn)換速率： | 1.8 V/µs |
| 增益帶寬積： | 1MHz |
| 電流 - 輸入偏壓： | 5pA |
| 電壓 - 輸入偏移： | 750µV |
| 電流 - 電源： | 340µA |
| 電流 - 輸出 / 通道： | 15mA |
| 電壓 - 電源，單路/雙路(±)： | ±4.5 V ~ 18 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 8-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 8-PDIP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁(yè)面： | 773 (CN2011-ZH PDF) |
AD648
REV. E
–7–
APPLICATION NOTES
The AD648 is a pair of JFET-input op amps with a guaranteed
maximum IB of less than 10 pA, and offset and drift laser-
trimmed to 1.0 mV and 10
V/°C, respectively (AD648B). AC
specs include 1 MHz bandwidth, 1.8 V/
s typical slew rate and
8
s settling time for a 20 V step to ±0.01%—all at a supply
current less than 400
A. To capitalize on the device’s perfor-
mance, a number of error sources should be considered.
The minimal power drain and low offset drift of the AD648
reduce self-heating or “warm-up” effects on input offset voltage,
making the AD648 ideal for on/off battery powered applica-
tions. The power dissipation due to the AD648’s 400
A supply
current has a negligible effect on input current, but heavy out-
put loading will raise the chip temperature. Since a JFET’s
input current doubles for every 10
°C rise in chip temperature,
this can be a noticeable effect.
The amplifier is designed to be functional with power supply
voltages as low as
±4.5 V. It will exhibit a higher input offset
voltage than at the rated supply voltage of
±15 V, due to power
supply rejection effects. Common-mode range extends from 3 V
more positive than the negative supply to 1 V more negative
than the positive supply. Designed to cleanly drive up to 10 k
and 100 pF loads, the AD648 will drive a 2 k
load with reduced
open-loop gain.
Figure 21 shows the recommended crosstalk test circuit. A
typical value for crosstalk is –120 dB at 1 kHz.
Figure 21. Crosstalk Test Circuit
LAYOUT
To take full advantage of the AD648’s 10 pA max input current,
parasitic leakages must be kept below an acceptable level. The
practical limit of the resistance of epoxy or phenolic circuit
board material is between 1
× 1012 and 3 × 1012 . This can
result in an additional leakage of 5 pA between an input of 0 V
and a –15 V supply line. Teflon or a similar low leakage material
(with a resistance exceeding 10
17
) should be used to isolate
high impedance input lines from adjacent lines carrying high
voltages. The insulator should be kept clean, since contaminants
will degrade the surface resistance.
A metal guard completely surrounding the high impedance
nodes and driven by a voltage near the common-mode input
potential can also be used to reduce some parasitic leakages.
The guarding pattern in Figure 22 will reduce parasitic leakage
due to finite board surface resistance; but it will not compensate
for a low volume resistivity board.
Figure 22. Board Layout for Guarding Inputs
INPUT PROTECTION
The AD648 is guaranteed to withstand input voltages equal to
the power supply potential. Exceeding the negative supply volt-
age on either input will forward bias the substrate junction of
the chip. The induced current may destroy the amplifier due to
excess heat.
Input protection is required in applications such as a flame
detector in a gas chromatograph, where a very high potential
may be applied to the input terminals during a sensor fault
condition. Figures 23a and 23b show simple current limiting
schemes that can be used. RPROTECT should be chosen such that
the maximum overload current is 1.0 mA (for example 100 k
for a 100 V overload).
Figure 23a. Input Protection of l-to-V Converter
Figure 23b. Voltage Follower Input Protection Method
Figure 23b shows the recommended method for protecting a
voltage follower from excessive currents due to high voltage
breakdown. The protection resistor, RP, limits the input current.
A nominal value of 100 k
will limit the input current to less
than 1 mA with a 100 volt input voltage applied.
The stray capacitance between the summing junction and
ground will produce a high-frequency roll-off with a corner
frequency equal to:
fcorner
=
1
2
π RP Cstray
Accordingly, a 100 k
value for RP with a 3 pF Cstray will cause
a 3 dB corner frequency to occur at 531 kHz.
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| TSW-123-06-T-S | CONN HEADER 23POS .100" SNGL TIN |
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| 9-146282-0-21 | CONN HDR BRKWAY .100 21POS VERT |
| 4-103741-0-21 | CONN HEADR BRKWAY .100 21POS STR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD648JNZKL1 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD648JR | 制造商:Analog Devices 功能描述:OP Amp Dual GP ±18V 8-Pin SOIC N 制造商:Rochester Electronics LLC 功能描述:LOW POWER DUAL OP AMP IC - Bulk 制造商:Analog Devices 功能描述:IC OP-AMP DUAL BIFET |
| AD648JR-REEL | 制造商:Analog Devices 功能描述:OP Amp Dual GP ±18V 8-Pin SOIC N T/R |
| AD648JR-REEL7 | 制造商:Analog Devices 功能描述:OP Amp Dual GP ±18V 8-Pin SOIC N T/R |
| AD648JRZ | 功能描述:IC OPAMP BIFET 1MHZ DUAL 8SOIC RoHS:是 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 產(chǎn)品培訓(xùn)模塊:Differential Circuit Design Techniques for Communication Applications 標(biāo)準(zhǔn)包裝:1 系列:- 放大器類型:RF/IF 差分 電路數(shù):1 輸出類型:差分 轉(zhuǎn)換速率:9800 V/µs 增益帶寬積:- -3db帶寬:2.9GHz 電流 - 輸入偏壓:3µA 電壓 - 輸入偏移:- 電流 - 電源:40mA 電流 - 輸出 / 通道:- 電壓 - 電源，單路/雙路(±):3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VQFN 裸露焊盤，CSP 供應(yīng)商設(shè)備封裝:16-LFCSP-VQ 包裝:剪切帶 (CT) 產(chǎn)品目錄頁(yè)面:551 (CN2011-ZH PDF) 其它名稱:ADL5561ACPZ-R7CT |
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