- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373889 > AD6472 (Analog Devices, Inc.) 2 Pair/1 Pair ETSI Compatible HDSL Analog Front End(2對(duì)/1對(duì)的符合ETSI標(biāo)準(zhǔn)的HDSL模擬前端處理器) PDF資料下載
參數(shù)資料
| 型號(hào)： | AD6472 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 2 Pair/1 Pair ETSI Compatible HDSL Analog Front End(2對(duì)/1對(duì)的符合ETSI標(biāo)準(zhǔn)的HDSL模擬前端處理器) |
| 中文描述： | 2對(duì)/ 1對(duì)ETSI兼容HDSL模擬前端（2對(duì)/ 1對(duì)的符合ETSI標(biāo)準(zhǔn)的HDSL模擬前端處理器） |
| 文件頁(yè)數(shù)： | 1/8頁(yè) |
| 文件大?。?/td> | 102K |
| 代理商： | AD6472 |
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD6472
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 1998
2 Pair/1 Pair ETSI Compatible
HDSL Analog Front End
FUNCT IONAL BLOCK DIAGRAM
CONTROL
LOGIC
12-BIT
DAC
2
7-BIT
DAC
12-BIT
ADC
2
BUFFER
2
ANALOG
FILTER
2
PGA
2
HYBRID
CIRCUIT
2
ANALOG
FILTER
2
DRIVER
2
2
TX_GAIN
TO
VCXO
T
X
R
X
3
AD6472
FEATURES
Integrated Front End for Single Pair or Two Pair HDSL
Systems
Meets ETSI Specifications
Supports 1168 Kbps and 2.32 Mbps
Transmit and Receive Signal Path Functions
Receive Hybrid Amplifier, PGA and ADC
Transmit DAC, Filter and Differential Outputs
Programmable Filters
Control and Ancillary Functions
Timing Recovery DAC
Normal Loopback and Low Power Modes
Simple Interface-to-Digital Transceivers
Single 5 V Power Supply
Power Consumption: 320 mW—(Excluding Driver)
Package: 80-Lead MQFP
Operating Temperature: –40
8
C to +85
8
C
GE NE RAL DE SCRIPT ION
T he AD6472 is a single chip analog front end for two pair or
single pair HDSL applications that use 1168 K bps or 2.32 Mbps
data rates.
T he AD6472 integrates all the transmit and receive functional
blocks together with the timing recovery DAC.
T he digital interface is designed to support industry standard
digital transceivers.
While providing the full analog front end for ET SI standards
(two pair or single pair HDSL applications) the AD6472 sup-
ports other applications because the architecture allows for
bypassing the functional blocks.
T he normal, low power, and loopback modes and the digital
interface combine to make the AD6472 simple to integrate into
systems.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD648A | Dual Precision, Low Power BiFET Op Amp |
| AD648JN | CAP X7R,0.1UF,50V,10%,0805 |
| AD648JR | Dual Precision, Low Power BiFET Op Amp |
| AD648JR-REEL | CAPACITOR 0805 X7R 10NF 100V 10%CAPACITOR 0805 X7R 10NF 100V 10%; CAPACITANCE:10NF; VOLTAGE RATING, DC:100V; CAPACITOR DIELECTRIC TYPE:CERAMIC MULTI-LAYER; SERIES:B37941; TOLERANCE, :10%; TOLERANCE, -:10%; TEMP, OP. MAX:125(DEGREE RoHS Compliant: Yes |
| AD648JR-REEL7 | Dual Precision, Low Power BiFET Op Amp |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD6472BS | 制造商:AD 制造商全稱:Analog Devices 功能描述:2 Pair/1 Pair ETSI Compatible HDSL Analog Front End |
| AD6472BSZ | 制造商:Analog Devices 功能描述: |
| AD647J | 制造商:AD 制造商全稱:Analog Devices 功能描述:Ultralow Drift, Dual BiFET Op Amp |
| AD647JH | 制造商:Rochester Electronics LLC 功能描述:PRECISION DUAL OP AMP IC - Bulk 制造商:ANALOG 功能描述:AD647JH 制造商:Analog Devices 功能描述: |
| AD647K | 制造商:AD 制造商全稱:Analog Devices 功能描述:Ultralow Drift, Dual BiFET Op Amp |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。