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參數(shù)資料
| 型號(hào)： | AD6458ARS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | GSM 3 V Receiver IF Subsystem |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO20 |
| 封裝： | SSOP-20 |
| 文件頁(yè)數(shù)： | 10/12頁(yè) |
| 文件大?。?/td> | 268K |
| 代理商： | AD6458ARS |
AD6458
–10–
REV. 0
PRODUCT OVERVIEW
The AD6458 provides most of the active circuitry required to
realize a complete low power, single-conversion superhetero-
dyne receiver, or the latter part of a double-conversion receiver,
at input frequencies up to 400 MHz, with an IF from 5 MHz to
50 MHz. The internal I/Q demodulators, and their associated
phase-locked loop, support a wide variety of modulation modes,
including n-PSK, n-QAM, and GMSK. A single positive supply
voltage of 3.3 V is required (3.0 V minimum, 3.6 V maximum)
at a typical supply current of 9 mA at midgain. In the following
discussion, V
POS
will be used to denote the power supply volt-
age, which will be assumed to be 3.3 V.
Figure 31 shows the main sections of the AD6458. It consists of
a variable-gain UHF mixer and linear two-stage IF strip, which
together provide a calibrated voltage-controlled gain range of
more than 76 dB, followed by dual quadrature demodulators.
These are driven by inphase and quadrature clocks generated by
a Phase-Locked Loop (PLL), which is locked to a corrected
external reference. A CMOS-compatible power-down interface
completes the AD6458.
V
GAIN
– Volts
V
P
2.0
1.9
1.00
2.5
0.5
1.0
1.5
2.0
1.6
1.3
1.2
1.1
1.8
1.7
1.4
1.5
T
A
= –40
°
C
T
A
= –25
°
C
T
A
= +25
°
C
T
A
= +85
°
C
Figure 29. Minimum Power-Up Voltage vs V
GAIN
, V
POS
=
3.0 V, V
REF
= 1.2 V
Mixer
The UHF mixer is an improved Gilbert-cell design, and can
operate from low frequencies (it is internally dc-coupled) up to
an RF input of 400 MHz. The dynamic range at the input of the
mixer is determined at the upper end by the maximum input
signal level of
±
56 mV (–15 dBm in 50
between RFHI and
RFLO) up to which the mixer remains linear and, at the lower
end, by the noise level. It is customary to define the linearity of
a mixer in terms of the 1 dB gain-compression point and third-
order intercept, which for the AD6458 are –12 dBm and
–2 dBm, respectively, in a 50
system.
The mixer’s RF input port is differential; that is, pin RFLO is
functionally identical to RFHI, and these nodes are internally
biased. The RF port can be modeled as a parallel RC circuit as
shown in Figure 30.
RFHI
RFLO
C
SH
R
SH
Figure 30. Mixer Port Modeled as a Parallel RC Network
The local oscillator (LO) input is internally biased at V
P
– 0.8 V
and must be ac coupled. The LO interface includes a preampli-
fier which minimizes the drive requirements, thus simplifying
the oscillator design and reducing LO leakage from the RF port.
The LO requires a single-sided drive of
±
50 mV, or –16 dBm in
a 50
system. For operation above 300 MHz noise figure can
be improved by increasing the LO level.
The output of the mixer is single ended with a 330
impedance
for driving ceramic filters.
The conversion gain is measured between the mixer input and
the input of this filter, and varies between –9 dB and +10 dB as
a function of the voltage at Pin GAIN.
The maximum permissible signal level at Pin MXOP is deter-
mined by the maximum gain control voltage.
The mixer output port is shown in Figure 32.
VPS1
RFHI
AD6458
MXOP
IFIP
IFIM
0
°
90
°
4.7k
4.7k
4.7k
4.7k
AGC VOLTAGE
BIAS
CIRCUIT
VPS2
PRUP
RFLO
LOIP
4
IRXP
IRXN
FREF
FLTR
QRXP
QRXN
GAIN
GREF
19
20
13
14
15
16
18
6
7
8
1
2
3
5
COM1
COM2
9
12
RF INPUT
–95dBm TO
–15dBm
330
0.1μF
LO INPUT
–16dBm
17
11
GAIN TC
COMPENSATION
PLL
13MHz
CERAMIC
FILTER
Figure 31. Functional Block Diagram
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD6459 | 制造商:AD 制造商全稱:Analog Devices 功能描述:GSM 3 V Receiver IF Subsystem |
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| AD6459ARS-REEL | 制造商:Analog Devices 功能描述:RF Receiver N-QAM/N-PSK/TDMA 3.3V/5V 20-Pin SSOP T/R |
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