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參數(shù)資料
| 型號： | AD6402 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | IF Transceiver Subsystem |
| 中文描述： | 中頻收發(fā)子系統(tǒng) |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 110K |
| 代理商： | AD6402 |
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD6402
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
Analog Devices, Inc., 1997
IF Transceiver Subsystem
FEATURES
On-Chip Regulator
PLL Demodulator
On-Chip VCO
No Trims
Excellent Sensitivity
28-Lead SSOP Package
APPLICATIONS
DECT/PWT/WLAN
TDMA FM/FSK Systems
GE NE RAL DE SCRIPT ION
T he AD6402 is a complete transceiver subsystem for use in
high bit rate radio systems employing FM or FSK modulation.
It is optimized for use in time domain multiple access (T DMA)
systems with communications rates of approximately 1 MBPS.
T he AD6402 integrates key functions, including VCOs and a
low drop-out voltage regulator. T he AD6402 operates directly
from an unregulated battery supply of 3.1 V to 4.5 V and pro-
vides a regulated voltage output which can be used for VCO
supply regulation on a companion RF chip such as the AD6401.
T he AD6402 transceiver consists of a mixer, integrated IF
bandpass filter, IF limiter with RSSI detection, VCO, PLL
demodulator and a low dropout voltage regulator. On receive, it
downconverts an IF signal in the 110 MHz range to a second
IF frequency, this frequency being determined by the demodu-
lator reference divide ratios. It then filters, amplifies, and de-
modulates this signal. T he AD6402 provides a filtered baseband
FUNCT IONAL BLOCK DIAGRAM
PLL
DEMOD
1
IF
VCO
VOLTAGE
REGULATOR
V
REF
MODE
CONTROL
DC
OFFSET
COMP
LIMITER/FILTER
2
AD6402
RSSI
CFILT
DOUT
DFILP
PLLOUT
FMMOD2
FMMOD1
IFIN
TXOUT
TXOUTB
VCO
VREG VBATT SLREF
CTL1...3
MODOUT
REFSEL
COFF
REFIN
data output. On transmit, it accepts a Gaussian Frequency Shift
K eying (GFSK ) baseband signal, low-pass filters the signal if
required using the on-chip op amp and modulates the IF VCO
by varying the bias voltage on an off-chip varactor diode used in
the tank circuit.
T he AD6402 has multiple power-down modes to maximize
battery life. It operates over a temperature range of –25
°
C to
+85
°
C and is packaged in a JEDEC standard 28-lead small-
shrink outline (SSOP) surface-mount package.
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