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參數(shù)資料
| 型號(hào)： | AD633ARZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/21頁 |
| 文件大小： | 0K |
| 描述： | IC MULTIPLIER ANALOG 8-SOIC T/R |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 功能： | 模擬乘法器 |
| 位元/級(jí)數(shù)： | 四象限 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SO |
| 包裝： | 帶卷 (TR) |
Data Sheet
AD633
Rev. J | Page 11 of 20
For example, if R = 8 kΩ and C = 0.002 F, then Output A has a
pole at frequencies from 100 Hz to 10 kHz for EC ranging from
100 mV to 10 V. Output B has an additional 0 at 10 kHz (and
can be loaded because it is the low impedance output of the
multiplier). The circuit can be changed to a high-pass filter Z
interchanging the resistor and capacitor as shown in Figure 21.
AD633JN
X1
1
X2
2
Y1
3
Y2
4
+VS 8
W
7
Z
6
–VS 5
CONTROL
INPUT EC
SIGNAL
INPUT ES
0.1F
+15V
–15V
00786-
020
R
C
OUTPUT B
OUTPUT A
dB
f1 f2
f
+6dB/OCTAVE
OUTPUT A
OUTPUT B
0
Figure 21. Voltage-Controlled, High-Pass Filter
VOLTAGE-CONTROLLED QUADRATURE OSCILLATOR
Figure 22 shows two multipliers being used to form integrators
with controllable time constants in second-order differential
equation feedback loop. R2 and R5 provide controlled current
output operation. The currents are integrated in capacitors C1
and C2, and the resulting voltages at high impedance are applied
to the X inputs of the next AD633. The frequency control input,
EC, connected to the Y inputs, varies the integrator gains with a
calibration of 100 Hz/V. The accuracy is limited by the Y input
offsets. The practical tuning range of this circuit is 100:1. C2
(proportional to C1 and C3), R3, and R4 provide regenerative
feedback to start and maintain oscillation. The diode bridge, D1
through D4 (1N914s), and Zener diode D5 provide economical
temperature stabilization and amplitude stabilization at ±8.5 V
by degenerative damping. The output from the second integrator
(10 V sin ωt) has the lowest distortion.
AUTOMATIC GAIN CONTROL (AGC) AMPLIFIERS
Figure 23 shows an AGC circuit that uses an rms-to-dc
converter to measure the amplitude of the output waveform.
The AD633 and A1, of an AD712 dual op amp, form a
voltage-controlled amplifier. The rms-to-dc converter, an
AD736, measures the rms value of the output signal. Its output
drives A2, an integrator/comparator whose output controls the
gain of the voltage-controlled amplifier. The 1N4148 diode
prevents the output of A2 from going negative. R8, a 50 kΩ
variable resistor, sets the output level of the circuit. Feedback
around the loop forces the voltages at the inverting and
noninverting inputs of A2 to be equal, thus the AGC.
AD633JN
X1
1
X2
2
Y1
3
Y2
4
+VS 8
W
7
Z
6
–VS 5
0.1F
C1
0.01F
+15V
–15V
AD633JN
X1
1
X2
2
Y1
3
Y2
4
+VS 8
W
7
Z
6
–VS 5
0.1F
+15V
–15V
R5
16k
R3
330k
R4
16k
C3
0.01F
C2
0.01F
(10V) sin ωt
0.1F
R2
16k
R1
1k
D5
1N5236
D1
1N914
D2
1N914
D3
1N914
D4
1N914
f =
EC
10V
= kHz
(10V) cos ωt
EC
00786-
021
Figure 22. Voltage-Controlled Quadrature Oscillator
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| AD633JN | 功能描述:IC ANALOG MULTIPLIER 8-DIP RoHS:否 類別:集成電路 (IC) >> 線性 - 模擬乘法器，除法器 系列:- 標(biāo)準(zhǔn)包裝:25 系列:HA 功能:模擬乘法器 位元/級(jí)數(shù):四象限 封裝/外殼:16-CDIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:16-CDIP 側(cè)面銅焊 包裝:管件 |
| AD633JNZ | 功能描述:IC ANALOG MULTIPLIER 8-DIP RoHS:是 類別:集成電路 (IC) >> 線性 - 模擬乘法器，除法器 系列:- 標(biāo)準(zhǔn)包裝:25 系列:HA 功能:模擬乘法器 位元/級(jí)數(shù):四象限 封裝/外殼:16-CDIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:16-CDIP 側(cè)面銅焊 包裝:管件 |
| AD633JR | 功能描述:IC ANALOG MULTIPLIER 8-SOIC RoHS:否 類別:集成電路 (IC) >> 線性 - 模擬乘法器，除法器 系列:- 標(biāo)準(zhǔn)包裝:25 系列:HA 功能:模擬乘法器 位元/級(jí)數(shù):四象限 封裝/外殼:16-CDIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:16-CDIP 側(cè)面銅焊 包裝:管件 |
| AD633JR | 制造商:Analog Devices 功能描述:SEMICONDUCTORSLINEAR |
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