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參數(shù)資料
| 型號： | AD633-EVALZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 1/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD633 |
| 標準包裝： | 1 |
| 主要目的： | 模擬乘法器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD633 |
| 主要屬性： | 四象限乘法 |
| 已供物品： | 板 |
Low Cost
Analog Multiplier
Data Sheet
Rev. J
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
Tel: 781.329.4700
2012–2013 Analog Devices, Inc. All rights reserved.
FEATURES
4-quadrant multiplication
Low cost, 8-lead SOIC and PDIP packages
Complete—no external components required
Laser-trimmed accuracy and stability
Total error within 2% of full scale
Differential high impedance X and Y inputs
High impedance unity-gain summing input
Laser-trimmed 10 V scaling reference
APPLICATIONS
Multiplication, division, squaring
Modulation/demodulation, phase detection
Voltage-controlled amplifiers/attenuators/filters
FUNCTIONAL BLOCK DIAGRAM
1
A
1
10V
0
07
86-
023
X1
X2
Y1
Y2
W
Z
Figure 1.
GENERAL DESCRIPTION
The AD633 is a functionally complete, four-quadrant, analog
multiplier. It includes high impedance, differential X and Y inputs,
and a high impedance summing input (Z). The low impedance
output voltage is a nominal 10 V full scale provided by a buried
Zener. The AD633 is the first product to offer these features in
modestly priced 8-lead PDIP and SOIC packages.
The AD633 is laser calibrated to a guaranteed total accuracy of
2% of full scale. Nonlinearity for the Y input is typically less
than 0.1% and noise referred to the output is typically less than
100 μV rms in a 10 Hz to 10 kHz bandwidth. A 1 MHz bandwidth,
20 V/μs slew rate, and the ability to drive capacitive loads make
the AD633 useful in a wide variety of applications where
simplicity and cost are key concerns.
The versatility of the AD633 is not compromised by its simplicity.
The Z input provides access to the output buffer amplifier, enabling
the user to sum the outputs of two or more multipliers, increase
the multiplier gain, convert the output voltage to a current, and
configure a variety of applications.
The AD633 is available in 8-lead PDIP and SOIC packages. It is
specified to operate over the 0°C to 70°C commercial temperature
range (J Grade) or the 40°C to +85°C industrial temperature
range (A Grade).
PRODUCT HIGHLIGHTS
1.
The AD633 is a complete four-quadrant multiplier offered
in low cost 8-lead SOIC and PDIP packages. The result is a
product that is cost effective and easy to apply.
2.
No external components or expensive user calibration are
required to apply the AD633.
3.
Monolithic construction and laser calibration make the
device stable and reliable.
4.
High (10 MΩ) input resistances make signal source
loading negligible.
5.
Power supply voltages can range from ±8 V to ±18 V. The
internal scaling voltage is generated by a stable Zener diode;
multiplier accuracy is essentially supply insensitive.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD633JN | 功能描述:IC ANALOG MULTIPLIER 8-DIP RoHS:否 類別:集成電路 (IC) >> 線性 - 模擬乘法器，除法器 系列:- 標準包裝:25 系列:HA 功能:模擬乘法器 位元/級數(shù):四象限 封裝/外殼:16-CDIP（0.300"，7.62mm） 供應商設備封裝:16-CDIP 側面銅焊 包裝:管件 |
| AD633JNZ | 功能描述:IC ANALOG MULTIPLIER 8-DIP RoHS:是 類別:集成電路 (IC) >> 線性 - 模擬乘法器，除法器 系列:- 標準包裝:25 系列:HA 功能:模擬乘法器 位元/級數(shù):四象限 封裝/外殼:16-CDIP（0.300"，7.62mm） 供應商設備封裝:16-CDIP 側面銅焊 包裝:管件 |
| AD633JR | 功能描述:IC ANALOG MULTIPLIER 8-SOIC RoHS:否 類別:集成電路 (IC) >> 線性 - 模擬乘法器，除法器 系列:- 標準包裝:25 系列:HA 功能:模擬乘法器 位元/級數(shù):四象限 封裝/外殼:16-CDIP（0.300"，7.62mm） 供應商設備封裝:16-CDIP 側面銅焊 包裝:管件 |
| AD633JR | 制造商:Analog Devices 功能描述:SEMICONDUCTORSLINEAR |
| AD633JR-REEL | 功能描述:IC MULTIPLIER ANALOG 8-SOIC T/R RoHS:否 類別:集成電路 (IC) >> 線性 - 模擬乘法器，除法器 系列:- 標準包裝:25 系列:HA 功能:模擬乘法器 位元/級數(shù):四象限 封裝/外殼:16-CDIP（0.300"，7.62mm） 供應商設備封裝:16-CDIP 側面銅焊 包裝:管件 |
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