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參數(shù)資料
| 型號： | AD6271 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 運(yùn)動控制電子 |
| 英文描述： | 10 MHz, 20 V/レs, G = 1, 10, 100, 1000 i CMOS㈢ Programmable Gain Instrumentation Amplifier |
| 中文描述： | 10兆赫，20第V /レ秒，增益\u003d 1，10，100，1000 i的CMOS㈢可編程增益儀表放大器 |
| 文件頁數(shù)： | 9/10頁 |
| 文件大?。?/td> | 228K |
| 代理商： | AD6271 |
Preliminary Technical Data
AD8253
Table 5. Truth Table Logic Levels for Transparent Gain Mode
WR
A1
A0
V
S
Low
Low
V
S
Low
High
V
S
High
Low
V
S
High
High
Rev. prA | Page 9 of 10
Gain
1
10
100
1000
Latched Gain Mode
Some applications have multiple programmable devices such as
multiplexers or other programmable gain instrumentation
amplifiers on the same PCB. In such cases, devices can share a
data bus. The gain of the AD8253 can be set using WR as a latch,
allowing other devices to share A0 and A1. Figure 7 shows a
schematic using this method, known as latched gain mode. The
AD8253 is in this mode when WR is held at logic high or logic
low, typically 5 V and 0 V, respectively. The voltages on A0 and
A1 are read on the downward edge of the WR signal as it
transitions from logic high to logic low. This latches in the logic
levels on A0 and A1, resulting in a gain change. See the truth
table listing in Table 6 for more on these gain changes.
Figure 7. Latched Gain Mode, G = 1000
Table 6. Truth Table Logic Levels for Latched Gain Mode
WR
A1
A0
High to Low
Low
Low
High to Low
Low
High
High to Low
High
Low
High to Low
High
High
Low to Low
X
1
X
1
Low to High
X
1
X
1
High to High
X
1
X
1
1
X = don’t care.
Upon power-up, the AD8253 defaults to a gain of 1 when in
latched gain mode. In contrast, if the AD8253 is configured in
transparent gain mode, it starts at the gain indicated by the
voltage levels on A0 and A1 upon power-up.
Timing for Latched Gain Mode
In latched gain mode, logic levels at A0 and A1 have to be held
for a minimum setup time, t
SU
, before the downward edge of
WR latches in the gain. Similarly, they must be held for a
minimum hold time of t
HD
after the downward edge of WR to
ensure that the gain is latched in correctly. After t
HD
, A0 and A1
may change logic levels but the gain does not change (until the
next downward edge of WR). The minimum duration that WR
can be held high is t
WR
-HIGH
, and t
WR
-LOW
is the minimum
duration that WR can be held low. Digital timing specifications
are listed in Table 2. The time required for a gain change is
dominated by the settling time of the amplifier. A timing
diagram is shown in Figure 8.
When sharing a data bus with other devices, logic levels applied
to those devices can potentially feed through to the output of
the AD8253. Feedthrough can be minimized by decreasing the
edge rate of the logic signals. Furthermore, careful layout of the
PCB also reduces coupling between the digital and analog
portions of the board.
Gain
Change to 1
Change to 10
Change to 100
Change to 1000
No Change
No Change
No Change
A0, A1
WR
t
SU
t
HD
t
WR-HIGH
t
WR-LOW
0
Figure 8. Timing Diagram for Latched Gain Mode
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