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參數(shù)資料
型號: AD625AD
廠商: Analog Devices Inc
文件頁數(shù): 6/15頁
文件大?。?/td> 0K
描述: IC AMP INST 25MHZ LN 16CDIP
產(chǎn)品變化通告: Product Discontinuance 27/Oct/2011
標(biāo)準(zhǔn)包裝: 23
放大器類型: 儀表
電路數(shù): 1
轉(zhuǎn)換速率: 5 V/µs
增益帶寬積: 25MHz
-3db帶寬: 650kHz
電流 - 輸入偏壓: 30nA
電壓 - 輸入偏移: 50µV
電流 - 電源: 3.5mA
電壓 - 電源,單路/雙路(±): ±6 V ~ 18 V
工作溫度: -40°C ~ 85°C
安裝類型: 通孔
封裝/外殼: 16-CDIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 16-CDIP 側(cè)面銅焊
包裝: 管件
AD625
REV. D
–14–
GAIN
1000
1
SETTLING
TIME
s
800
400
200
100
80
40
20
10
8
4
2
1
4
16
64
256
1024
4096
RON = 1k
RON = 500
RON = 200
RON = 0
Figure 40. Time to 0.01% of a 20 V Step Input for
SPGA with AD625
DETERMINING SPGA RESISTOR NETWORK VALUES
The individual resistors in the gain network can be calculated
sequentially using the formula given below. The equation deter-
mines the resistors as labeled in Figure 41. The feedback resis-
tors and the gain setting resistors are interactive, therefore; the
formula must be a series where the present term is dependent on
the preceding term(s). The formula
Rk
R
G
R
Fi
Fj
j
i
F
+
=
1
0
1
0
20
1
0
(
)( –
)
can be used to calculate the necessary feedback resistors for any
set of gains. This formula yields a network with a total resistance
of 40 k
. A dummy variable (j) serves as a counter to keep a
running total of the preceding feedback resistors. To illustrate
how the formula can be applied, an example similar to the
calculation used for the resistor network in Figure 38 is exam-
ined below.
1) Unity gain is treated as a separate case. It is implemented
with separate 20 k
feedback resistors as shown in Figure 41.
It is then ignored in further calculations.
2) Before making any calculations it is advised to draw a resistor
network similar to the network in Figure 41. The network
will have (2
× M) + 1 resistors, where M = number of gains.
For Figure 38 M = 3 (4, 16, 64), therefore, the resistor string
will have seven resistors (plus the two 20 k
“side” resistors
for unity gain).
3) Begin all calculations with G0 = 1 and RF
0
= 0.
RF
1
= (20 k
– R
F0) (1–1/4): RF0 = 0 ∴ RF1 = 15 k
RF
2
= [20 k
– (R
F0 + RF1)] (1–4/16):
RF
0
+ RF
1
= 15 k
∴ R
F2 = 3.75 k
RF
3
= [20 k
– (R
F0 + RF1 + RF2)] (1–16/64):
RF
0
+ RF
1
+ RF
2
= 18.75 k
∴ R
F3 = 937.5
4) The center resistor (RG of the highest gain setting), is deter-
mined last. Its value is the remaining resistance of the 40 k
string, and can be calculated with the equation:
Rk
R
GFj
j
M
=
(
)
40
2
0
RG = 40 k
2 (R
F0 + RF1 + RF2 + RF3 )
40 k
– 39.375 k = 625
5) If different resistor values are desired, all the resistors in the
network can be scaled by some convenient factor. However,
raising the impedance will increase the RTO errors, lowering
the total network resistance below 20 k
can result in ampli-
fier instability. More information on this phenomenon is
given in the RPGA section of the data sheet. The scale factor
will not affect the unity gain feedback resistors. The resistor
network in Figure 38 has a scaling factor of 650/625 = 1.04,
if this factor is used on RF
1
, RF
2
, RF
3
, and RG, then the resis-
tor values will match exactly.
6) Round off errors can be cumulative, therefore, it is advised to
carry as many significant digits as possible until all the values
have been calculated.
AD75xx
TO GAIN SENSE
(PIN 2)
20k
RF1
20k
RF2
RFN
RFG
RFN
RF2
TO GAIN SENSE
(PIN 15)
TO GAIN DRIVE
(PIN 5)
TO GAIN DRIVE
(PIN 12)
CONNECT IF UNITY
GAIN IS DESIRED
CONNECT IF UNITY
GAIN IS DESIRED
Figure 41. Resistors for a Gain Setting Network
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