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REV. 0
AD6140
–4–
PIN FUNCTION DESCRIPTION
Pin
No
Pin
Name
Function
Applicable Signal Levels
1
2
3
LNA_FORCE
LNA_SENSE
CLK_IN+
Output For Biasing Discrete LNA
Input For Biasing Discrete LNA
Positive 6.144 MHz ADC Clock Input
Output Ranges from 0 V (LNA OFF) to 2.7 V
VDD to VDD – 0.3 V Input
800 mV p-p Differential Input
VDD to VDD – 0.8 V Levels
Direct Coupled into 1500
Impedance
800 mV p-p Differential Input
VDD to VDD – 0.8 V Levels
Direct Coupled into 1500
Impedance
Pin Connected to Ground
CMOS Logic Levels
CMOS Logic Levels
Digital Supply Input
CMOS Logic Levels; 0 V = ON, VPOS = OFF
CMOS Logic Levels; 0 V = Fast Mode,
VPOS = Slow Mode
4
CLK_IN–
Negative 6.144 MHz ADC Clock Input
5
6
7
8
9
10
BUFFER_GND
Σ
_DATA_OUT
Σ
_CLOCK_OUT
BUFFER_VDD
POWER_DOWN
AGC_TC_SELECT
ECL-to-CMOS Level Translator Ground
Σ
ADC Serial Data Output
6.144 MHz ADC Clock Output
ECL-to-CMOS Level Translator VDD
Turns IC Off and On
AGC Time Constant Select; Changes
AGC Capacitor Charging Current by 56:1,
where FAST AGC Current is 56
×
SLOW
AGC Current
Digital Power Supply Input
Digital Ground
Charge/Discharge Current into AGC
Integrator Capacitor
Positive LO Input
11
12
13
DVDD
DGND
AGC_CAPACITOR
Pin Connected to Digital Supply
Pin Connected to Ground
AGC Integration Capacitor
Connected to Ground
200 mV p-p Differential Input; Internally
AC-Coupled into 1500
Impedance
200 mV p-p Differential Input, Internally
AC-Coupled into 1500
Impedance
39 k
Resistor Connected to Ground
14
LO_IN+
15
LO_IN–
Negative LO Input
16
BIAS_RESISTOR
Resistor to Ground Sets Overall Bias
Current and Power Consumption
ADC Voltage Reference Input
Analog Ground
IF Input
Analog Power Supply Input
17
18
19
20
VOLTAGE_REFERENCE_IN
AGND
IF_INPUT
AVDD
Regulated and Filtered 1.0 V
±
5% Input
Pin Connected to Ground
Typically 16.4
μ
V p-p to 65.2 mV p-p
Pin Connected to Analog Supply