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參數(shù)資料
| 型號(hào)： | AD6121ACP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | 通信及網(wǎng)絡(luò) |
| 英文描述： | CDMA 3 V Receiver IF Subsystem with Integrated Voltage Regulator |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, QCC32 |
| 封裝： | 5 X 5 MM, MO-220VHHD-2, LPCC-32 |
| 文件頁(yè)數(shù)： | 13/16頁(yè) |
| 文件大?。?/td> | 258K |
| 代理商： | AD6121ACP |
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AD6121
–13–
REV. B
IFVCC
DGND
LOIPP
LOIPN
DVCC
LDOC
LDOB
LDOE
IFOPP
IFOPN
DEMIPN
DEMIPP
IOPP
IOPN
PD1
REFOUT
REFIN
VGAIN
LDOGND
VCC
2
I
Q
CDMA/FM
LOW
DROPOUT
REGULATOR
GAIN
CONTROL
SCALE
FACTOR
AD6121
CDMAIPN
CDMAIPP
IFGND
FMIPN
FMIPP
QOPP
QOPN
PD2
TEMP
COMP
I INPUT POS
I INPUT NEG
Q INPUT POS
Q INPUT NEG
EXT REF IN
RX AGC DAC
CDMA
BASEBAND
IC
1k
159nF
Figure 36. Typical Application Showing Interface to Baseband IC with SSOP Package
50
50
–
8.55dBm
REFERRED TO 50
236mV p-p
–
5.55dBm
REFERRED TO 100
472mV p-p
AD830
SPECTRUM
ANALYZER
–
19.6dBm DIFFERENTIAL
REFERRED TO 700
247.8mV p-p DIFFERENTIAL
LOCAL
OSCILLATOR INPUT
168.76MHz
100mV p-p DIFFERENTIAL
Z
IN
= 500
V
= 2.5V
GAIN = +41.4dB
Z
= 700
AT 85.38MHz
–
14dBm DIFFERENTIAL
REFERRED TO 700
472mV p-p DIFFERENTIAL
f = 85.38MHz
–
61dBm DIFFERENTIAL
REFERRED TO 500
1.78mV p-p DIFFERENTIAL
f = 85.38MHz
–
60dBm
REFERRED TO 50
632.5mV p-p DIFFERENTIAL
2
I
Q
IOUT
IOUT
QOUT
QOUT
50
50
AD830
1:8
1k
SIGNAL
GENERATOR
50
Figure 35. AD6121 Signal Level Diagram for AD6121 Customer Sample Board, Rev. B
OUTPUT INTERFACES
The AD6121 interfaces to CDMA baseband converters requir-
ing either IF or baseband inputs. The baseband output is pro-
vided by direct connection of the AD6121
’
s baseband output to
the baseband input of the baseband converter (Figure 36). The
output interfaces are controlled by the AD6121
’
s power-down
modes.
AD6121 CUSTOMER EVALUATION BOARD
The AD6121 customer evaluation board consists of an AD6121,
I/O connectors, 3 two-pin headers, a 20-pin dual header and
two AD830 High Speed Video Difference Amplifiers. It allows
the user to evaluate the AD6121
’
s I and Q demodulator and IF
amplifiers operating together or separately. The board is identical
for both the SSOP and LPCC packages. Because the AD6121 can
operate at any IF frequency from 50 MHz to 350 MHz, pads
are provided on the LOIPP, IFIP, CDMAIP and DMOD IN
inputs as well as the IF OUT output ports to allow the user to
add matching networks. The board is configured for an IF fre-
quency of 85.38 MHz when shipped.
The AD830s are used to provide differential to single ended
conversion for analysis of the differential I and Q outputs. As a
result, the output can be displayed on a spectrum analyzer or
other test equipment requiring a single ended input.
Prior to applying a CDMA or FM input signal, the appropriate
mode must be selected. FM mode will be selected by shorting
the two pins of the two pin header labeled FM/CDMA. Open
circuiting these two pins will select CDMA mode.
In order to test the power-down modes of the AD6121, locate
the bank of 3 two-pin headers on the evaluation board. In order
to have both the IF amplifiers and the I and Q demodulator
powered up, short circuit each of the two pins on the two pin
headers labeled PD1 and PD2. In order to power down the
demodulator and keep the IF amplifiers powered up, short
circuit the 2 pins on the header labeled PD1 and open circuit
相關(guān)PDF資料 |
PDF描述 |
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| AD6121ARS | CDMA 3 V Receiver IF Subsystem with Integrated Voltage Regulator |
| AD6121 | CDMA 3 V Receiver IF Subsystem with Integrated Voltage Regulator |
| AD6121ACPRL | CDMA 3 V Receiver IF Subsystem with Integrated Voltage Regulator |
| AD6122ARSRL | CDMA 3 V Transmitter IF Subsystem with Integrated Voltage Regulator |
| AD6122ARS | CDMA 3 V Transmitter IF Subsystem with Integrated Voltage Regulator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD6121ACPRL | 制造商:AD 制造商全稱:Analog Devices 功能描述:CDMA 3 V Receiver IF Subsystem with Integrated Voltage Regulator |
| AD6121ACPRL7 | 制造商:Analog Devices 功能描述: |
| AD6121ACPRL-7 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD6121ARS | 制造商:Analog Devices 功能描述: |
| AD6121ARSRL | 制造商:AD 制造商全稱:Analog Devices 功能描述:CDMA 3 V Receiver IF Subsystem with Integrated Voltage Regulator |
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