S/H Offset (V ) = 0.3 pC 100 pF + C EXT
參數(shù)資料
型號(hào): AD585AQ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 5/6頁(yè)
文件大?。?/td> 0K
描述: IC AMP SAMPLE HOLD 50MA 14CDIP
標(biāo)準(zhǔn)包裝: 25
放大器類型: 采樣和保持
電路數(shù): 1
轉(zhuǎn)換速率: 10 V/µs
-3db帶寬: 2MHz
電流 - 輸入偏壓: 2nA
電壓 - 輸入偏移: 2000µV
電流 - 電源: 10mA
電流 - 輸出 / 通道: 50mA
電壓 - 電源,單路/雙路(±): ±5 V ~ 18 V
工作溫度: -25°C ~ 85°C
安裝類型: 通孔
封裝/外殼: 14-CDIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 14-CERDIP
包裝: 管件
產(chǎn)品目錄頁(yè)面: 768 (CN2011-ZH PDF)
AD585
REV. A
–5–
For the AD585 in particular it becomes:
S/H Offset (V )
=
0.3 pC
100 pF
+ C
EXT
()
The addition of an external hold capacitor also affects the acqui-
sition time of the AD585. The change in acquisition time with
respect to the CEXT is shown graphically in Figure 2.
HOLD MODE
In the hold mode there are two important specifications that
must be considered; feedthrough and the droop rate. Feedthrough
errors appear as an attenuated version of the input at the output
while in the hold mode. Hold-Mode feedthrough varies with fre-
quency, increasing at higher frequencies. Feedthrough is an im-
portant specification when a sample and hold follows an analog
multiplexer that switches among many different channels.
Hold-mode droop rate is the change in output voltage per unit
of time while in the hold mode. Hold-mode droop originates as
leakage from the hold capacitor, of which the major leakage
current contributors are switch leakage current and bias current.
The rate of voltage change on the capacitor dV/dT is the ratio of
the total leakage current IL to the hold capacitance CH.
Droop Rate
=
dVOUT
dT
(Volts/Sec)
=
IL ( pA)
CH ( pF )
For the AD585 in particular;
Droop Rate
=
100 pA
100 pF
+ (C
EXT )
Additionally the leakage current doubles for every 10
°C increase
in temperature above 25
°C; therefore, the hold-mode droop rate
characteristic will also double in the same fashion. The hold-mode
droop rate can be traded-off with acquisition time to provide the
best combination of droop error and acquisition time. The tradeoff
is easily accomplished by varying the value of CEXT.
Since a sample and hold is used typically in combination with
an A/D converter, then the total droop in the output voltage has
to be less than 1/2 LSB during the period of a conversion. The
maximum allowable signal change on the input of an A/D
converter is:
V max =
Full -Scale Voltage
2
N
+1
()
Once the maximum
V is determined then the conversion time
of the A/D converter (TCONV) is required to calculate the maxi-
mum allowable dV/dT.
dV
dt
max
=
V max
TCONV
The maximum
dV max
dT
as shown by the previous equation is
the limit not only at 25
°C but at the maximum expected operat-
ing temperature range. Therefore, over the operating temperature
range the following criteria must be met (TOPERATION –25°C)
=
T.
dV 25
°C
dT
× 2
T °C
()
10
°C
≤ dV max
dT
HOLD-TO-SAMPLE TRANSITION
The Nyquist theorem states that a band-limited signal which is
sampled at a rate at least twice the maximum signal frequency
can be reconstructed without loss of information. This means
that a sampled data system must sample, convert and acquire
the next point at a rate at least twice the signal frequency. Thus
the maximum input frequency is equal to
f MAX =
1
2 T ACQ + TCONV + TAP
()
Where TACQ is the acquisition time of the sample-to-hold
amplifier, TAP is the maximum aperture time (small enough to
be ignored) and TCONV is the conversion time of the A/D
converter.
DATA ACQUISITION SYSTEMS
The fast acquisition time of the AD585 when used with a high
speed A/D converter allows accurate digitization of high fre-
quency signals and high throughput rates in multichannel data
acquisition systems. The AD585 can be used with a number of
different A/D converters to achieve high throughput rates. Fig-
ures 12 and 13 show the use of an AD585 with the AD578 and
AD574A.
Figure 12. A/D Conversion System, 117.6 kHz Throughput
58.8 kHz max Signal Input
Figure 13. 12-Bit A/D Conversion System, 26.3 kHz
Throughput Rate, 13.1 kHz max Signal Input
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